scholarly journals Absolute Difference and Low-Power Bus Encoding Method for LCD Digital Display Interfaces

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-6
Author(s):  
Chia-Hao Fang ◽  
I-tao Lung ◽  
Chih-Peng Fan
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Total Power ◽  
Absolute Difference ◽  
Digital Display ◽  
Power Bus ◽  
Differential Signaling ◽  
Bus Encoding ◽  
The Absolute ◽  
Encoding Method

Power dissipation has been an inevitable problem of LCD systems for years. To ease the problem, many encoding methods have been developed, such as the methods of transition minimized differential signaling, the most popular one in use for DVI to date, chromatic encoding, and limited intraword transition. In this paper, the authors present the absolute difference and low-power encoding method for the serial transmission of LCD digital DVI display interface. In regard to the LCD digital display interface with UMC 90 nm technology, the proposed method minimizes the architectural complexity and reduces the power dissipation by about 67% and 12%, respectively, compared with the transition minimized differential signaling and limited intraword transition. In short, the proposed method is an efficient bus encoding method to largely decrease the dynamic and total power dissipation of the LCD digital display interfaces.

scholarly journals Design of Low Power Transceiver on Spartan-3 and Spartan-6 FPGA

2019 ◽  
Vol 8 (12S2) ◽  
pp. 27-30
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Power Analysis ◽  
Research Work ◽  
Leakage Power ◽  
Total Power ◽  
Voltage Supply ◽  
Field Programmable ◽  
Eda Tools

In this research work, a low power transceiver is designed using Spartan-3 and Spartan-6 Field-Programmable Gate Array (FPGA). In this work, a Universal Asynchronous Receiver Transmitter (UART) device is used as a transceiver. The implementation of UART is possible with EDA tools called Xilinx 14.1 and the results of the power analysis are targeted on Spartan-3 and Spartan-6 FPGA. The variation of different power of chips that are fabricated on FPGA for e.g., Input/Output (I/O) power consumption, Leakage power dissipation, Signal power utilization, Logic power usage, and the use of Total power, is observed by changing the voltage supply. This research work shows how the change in voltage influence the power consumption of UART on Spartan-3 and Spartan-6 FPGA devices. It is observed that Spartan-6 is found to be more powerefficient as voltage supply increases.

Efficient RC low-power bus encoding methods for crosstalk reduction

Integration ◽  
2011 ◽  
Vol 44 (1) ◽  
pp. 75-86 ◽  
Author(s):  
Chih-Peng Fan ◽  
Chia-Hao Fang
Keyword(s):  
Low Power ◽  
Power Bus ◽  
Bus Encoding ◽  
Crosstalk Reduction

High-Swing, High-Resolution, Low-Power, Low-Area Voltage-Mode LTA/WTA Circuits

2015 ◽  
Vol 24 (07) ◽  
pp. 1550103 ◽  
Author(s):  
Mohammad Soleimani ◽  
Siroos Toofan ◽  
Mostafa Yargholi
Keyword(s):  
High Resolution ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Rank Order ◽  
Active Area ◽  
Total Power ◽  
Common Source ◽  
Cmos Process ◽  
Process Technology

In this paper, a general architecture for analog implementation of loser/winner-take-all (LTA/WTA) and other rank order circuits is presented. This architecture is composed of a differential amplifier with merged n-inputs and a merged common-source with active load (MCSAL) circuit to choose the desired input. The advantages of the proposed structure are simplicity, very high resolution, very low supply voltage requirements, very low output resistor, low power dissipation, low active area and simple expansion for multiple inputs by adding only three transistors for each extra input. The post-layout simulation results of proposed circuits are presented by HSPICE software in 0.35-μm CMOS process technology. The total power dissipation of proposed circuits is about 110-μW. Also, the total active area is about 550-μm2 for five-input proposed circuits, and would be negligibly increased for each extra input.

IMPROVED DYNAMIC CURRENT MODE LOGIC FOR LOW POWER APPLICATIONS

2008 ◽  
Vol 17 (02) ◽  
pp. 183-190 ◽  
Author(s):  
S. RAMAKRISHNAN ◽  
K. T. LAU
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
Power Dissipation ◽  
Current Mode ◽  
Total Power ◽  
Active Mode ◽  
Dynamic Power ◽  
Current Mode Logic ◽  
Low Power Dissipation ◽  
Standby Mode

In this paper, a newly improved dynamic current mode logic (I-DyCML) is proposed to achieve low power dissipation. The principle used in I-DyCML is the reduction of the leakage current by turning the part of the circuit to "standby mode", when not in use, while achieving lower dynamic power during the active mode. HSpice simulations show that I-DyCML saves up to 15–30% of the total power dissipation when compared to Dynamic Current mode logic.

scholarly journals DESIGN APPROACHES FOR LOW POWER- LOW AREA D FLIP FLOP S IN NANO TECHNOLOGY

2013 ◽  
pp. 231-236
Author(s):  
FAYAZ KHAN ◽  
SIREESH BABU
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Vital Role ◽  
Leakage Power ◽  
Total Power ◽  
Short Channel ◽  
Qualitative Comparison ◽  
Flip Flop ◽  
Low Area ◽  
Total Power Consumption

This paper enumerates design of D flip flop with low power and low area for low power applications, for that analysis of various D-flip flops for low power dissipation ,area and delays is carried out at 0.12um to achieve low power, low-area the technology is scaled down to nanometer ranges, due to shrinking process, the leakage power tends to play a vital role in total power consumption at nano meter technology. In this paper, different D flip flop circuits are designed using Berkeley Short Channel Insulated Gate MOSFET (BSIM4) model equations., in this paper to reduce leakage power at 90nm 70nm and 50nm we implement leakage power reduction techniques six techniques are considered they are namely Sleep transistor, sleepy stack, Dual sleep ,Dual stack Forced Transistor sleep (FTS) and Sleepy keeper From the results, it is observed that SLEEP TRANSISTOR, and SLEEPY KEEPER.FORCED TRANSISTOR SLEEP techniques produces lower power dissipation than the other techniques , in this paper a qualitative comparison is done with the help of Dsch,, Micro wind Simulation tools, this paper concludes that a leakage reduction technique produce different power optimization levels for different architectures and employing a suitable technique for a particular architecture will be an effective way of reducing the leakage current and thereby static power.

Positive and Negative Feedback for Linearity Improvement and PVT Compensation of the Ramp Generator

2018 ◽  
Vol 28 (02) ◽  
pp. 1950028 ◽  
Author(s):  
Mohsen Padash ◽  
Mostafa Yargholi
Keyword(s):  
Low Power ◽  
Negative Feedback ◽  
Power Dissipation ◽  
Total Power ◽  
Portable Devices ◽  
Analog To Digital ◽  
Ramp Generator ◽  
Generator Circuit ◽  
Positive Feedback Circuit ◽  
Linearity Improvement

Linearity of ramp signals is one of the most important aspects for many applications such as single-slope analog to digital converters (ADCs); another important aspect is the total power dissipation. Applications like high-resolution single-slope ADCs that can be used in portable devices demanded accurate ramp generator with low power dissipation. This paper presents a low power ramp generator with linearity improvement that achieved by a positive feedback circuit and negative feedback for compensation of the variations in process, voltage and temperature. Derived equations of the proposed ramp generator circuit show that linearity of the output ramp, with proper choosing of device sizes, can be enhanced significantly. Also, for proving of linearity enhancement, the circuit design and post-layout simulations were done in TSMC 0.18[Formula: see text][Formula: see text]m and 90[Formula: see text]nm CMOS technologies. Simulation results show that linearity of the circuit improved by a factor of 8 and total ramp resolution improved about 3 bit, whereas power dissipation of the circuit is about 8[Formula: see text][Formula: see text]W and entire layout core area is near 800[Formula: see text][Formula: see text]m2.

scholarly journals A CLASS OF IRREDUNDANT ENCODING TECHNIQUES FOR REDUCING BUS POWER

2002 ◽  
Vol 11 (05) ◽  
pp. 445-457 ◽  
Author(s):  
YAZDAN AGHAGHIRI ◽  
FARZAN FALLAH ◽  
MASSOUD PEDRAM
Keyword(s):  
Power Consumption ◽  
Power Dissipation ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Total Power ◽  
Switching Activity ◽  
Printed Circuit ◽  
Memory Address ◽  
Total Power Consumption ◽  
Bus Encoding

This paper proposes a number of encoding techniques for decreasing power dissipation on global buses. The best target for these techniques is a wide and highly capacitive memory bus. Switching activity of the bus is reduced by means of encoding the values that are conveyed over them. More precisely, three irredundant bus-encoding techniques are presented in this paper. These techniques decrease the bus activity by as much as 86% for instruction addresses without the need to add redundant bus lines. Having no redundancy means that exercising these techniques on any existing system does not require redesign and remanufacturing of the printed circuit board of the system. The power dissipation of the encoder and decoder blocks is insignificant in comparison with the power saved on the memory address bus. This makes these techniques capable of reducing the total power consumption.

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