Positive and Negative Feedback for Linearity Improvement and PVT Compensation of the Ramp Generator

2018 ◽  
Vol 28 (02) ◽  
pp. 1950028 ◽  
Author(s):  
Mohsen Padash ◽  
Mostafa Yargholi
Keyword(s):  
Low Power ◽  
Negative Feedback ◽  
Power Dissipation ◽  
Total Power ◽  
Portable Devices ◽  
Analog To Digital ◽  
Ramp Generator ◽  
Generator Circuit ◽  
Positive Feedback Circuit ◽  
Linearity Improvement

Linearity of ramp signals is one of the most important aspects for many applications such as single-slope analog to digital converters (ADCs); another important aspect is the total power dissipation. Applications like high-resolution single-slope ADCs that can be used in portable devices demanded accurate ramp generator with low power dissipation. This paper presents a low power ramp generator with linearity improvement that achieved by a positive feedback circuit and negative feedback for compensation of the variations in process, voltage and temperature. Derived equations of the proposed ramp generator circuit show that linearity of the output ramp, with proper choosing of device sizes, can be enhanced significantly. Also, for proving of linearity enhancement, the circuit design and post-layout simulations were done in TSMC 0.18[Formula: see text][Formula: see text]m and 90[Formula: see text]nm CMOS technologies. Simulation results show that linearity of the circuit improved by a factor of 8 and total ramp resolution improved about 3 bit, whereas power dissipation of the circuit is about 8[Formula: see text][Formula: see text]W and entire layout core area is near 800[Formula: see text][Formula: see text]m2.

An Opamp-Less PVT Compensation Structure for Ramp Generator Circuit

2020 ◽  
pp. 2150032
Author(s):  
Mohsen Padash ◽  
Mostafa Yargholi ◽  
Maryam Shojaei Baghini
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Power Dissipation ◽  
Feedback Loop ◽  
Cmos Technology ◽  
Compensation Structure ◽  
Ramp Generator ◽  
Generator Circuit ◽  
Low Power Dissipation ◽  
Ramp Signal

Accurate ramp signal, with low power dissipation, is highly demanded, for applications like counter ADC. This paper presents a novel low power ramp generator circuit with a negative feedback loop for compensation of the variations in process, voltage, and temperature (PVT). While using an opamp for PVT compensation has been essential in the previous ramp generator structures, the proposed ramp generator is opamp-less. Derived equations of the proposed ramp generator circuit show that PVT compensation structure works effectively. In addition, the circuit design and simulations were done in TSMC 0.18[Formula: see text][Formula: see text]m CMOS technology. Corner analysis shows that integral non-linearity (INL) of the ramp signal is about 3.7[Formula: see text]mV, for a wide temperature range, while the power dissipation of the circuit is about 1.16[Formula: see text][Formula: see text]W.

scholarly journals Memristor: A Unique Discovery for Reducing Power

2020 ◽  
Vol 9 (4) ◽  
pp. 1183-1187
Keyword(s):  
Low Power ◽  
Dominant Role ◽  
Reducing Power ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Leakage Power ◽  
Total Power ◽  
Portable Devices ◽  
Power Devices ◽  
Threshold Regime

A Process parameter variation has increasing, which results unpredictable device behaviour, due to occurrence of deep submicron CMOS technology. As the time passage this issue is exasperated by low power requirements which are approaching transistor operation into sub threshold regime. Principally for portable devices efficient, capable and process variation amiable memory is the most demandable in the market. In designing of low power memories, leakage power is observant parameter to design low power devices, because leakage power plays a dominant role in the total power utilization of the devices. In this paper, simple 6T SRAM formed with memristor has compared with the technique based 6T SRAM for the various parameters like total power and leakage power

scholarly journals Subthreshold Region based Linear Feedback Shift Register

2019 ◽  
Vol 8 (6S2) ◽  
pp. 817-821
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
System Level ◽  
Linear Feedback ◽  
Portable Devices ◽  
Subthreshold Region ◽  
Flip Flop ◽  
Ultra Low Power

Growing demand for portable devices and fast increases in complexity of chip cause power dissipation is an important parameter. Power consumption and dissipation or generations of more heat possess a restriction in the direction of the integration of more transistors. Several methods have been proposed to reduce power dissipation from system level to device level. Subthreshold circuits are widely used in more advanced applications due to ultra low-power consumption. The present work targets on construction of linear feedback shift registers (LFSR) in weak inversion region and their performance observed in terms of parameters like power delay product (PDP). In CMOS circuits subthreshold region of operation allows a low-power for ample utilizations but this advantage get with the penalty of flat speed. For the entrenched and high speed applications, improving the speed of subthreshold designs is essential. To enhance this, operate the devices at maximum current over capacitance. LFSR architectures build with various types of D flip flop and XOR gate circuits are analyzed. Circuit level Simulation is carried out using 130 nm technologies.

scholarly journals Design of Low Power Transceiver on Spartan-3 and Spartan-6 FPGA

2019 ◽  
Vol 8 (12S2) ◽  
pp. 27-30
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Power Analysis ◽  
Research Work ◽  
Leakage Power ◽  
Total Power ◽  
Voltage Supply ◽  
Field Programmable ◽  
Eda Tools

In this research work, a low power transceiver is designed using Spartan-3 and Spartan-6 Field-Programmable Gate Array (FPGA). In this work, a Universal Asynchronous Receiver Transmitter (UART) device is used as a transceiver. The implementation of UART is possible with EDA tools called Xilinx 14.1 and the results of the power analysis are targeted on Spartan-3 and Spartan-6 FPGA. The variation of different power of chips that are fabricated on FPGA for e.g., Input/Output (I/O) power consumption, Leakage power dissipation, Signal power utilization, Logic power usage, and the use of Total power, is observed by changing the voltage supply. This research work shows how the change in voltage influence the power consumption of UART on Spartan-3 and Spartan-6 FPGA devices. It is observed that Spartan-6 is found to be more powerefficient as voltage supply increases.

scholarly journals An Ultra-Low Power Parity Generator Circuit Based on QCA Technology

2019 ◽  
Vol 2019 ◽  
pp. 1-8 ◽  
Author(s):  
Ismail Gassoumi ◽  
Lamjed Touil ◽  
Bouraoui Ouni ◽  
Abdellatif Mtibaa
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Electrostatic Interactions ◽  
Cmos Technology ◽  
Power Parity ◽  
Ultra Low Power ◽  
Generator Circuit ◽  
Comparison Results ◽  
Low Power Dissipation ◽  
Parity Generator

Quantum-dot cellular automata (QCA) technology is one of the emerging technologies that can be used for replacing CMOS technology. It has attracted significant attention in the recent years due to its extremely low power dissipation, high operating frequency, and a small size. In this study, we demonstrate an n-bit parity generator circuit by utilizing QCA technology. Here, a novel XOR gate is used in the synthesis of the proposed circuit. The proposed gate is based on electrostatic interactions between cells to perform the desired function. The comparison results demonstrate that the designed QCA circuits have advantages compared to other circuits in terms of cell count, area, delay, and power consumption. The QCADesigner software, as widely used QCA circuit design and verification, has been used to implement and to verify all of the designs in this study. Power dissipation has been computed for the proposed circuit using accurate QCAPro power estimator tool.

High-Swing, High-Resolution, Low-Power, Low-Area Voltage-Mode LTA/WTA Circuits

2015 ◽  
Vol 24 (07) ◽  
pp. 1550103 ◽  
Author(s):  
Mohammad Soleimani ◽  
Siroos Toofan ◽  
Mostafa Yargholi
Keyword(s):  
High Resolution ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Rank Order ◽  
Active Area ◽  
Total Power ◽  
Common Source ◽  
Cmos Process ◽  
Process Technology

In this paper, a general architecture for analog implementation of loser/winner-take-all (LTA/WTA) and other rank order circuits is presented. This architecture is composed of a differential amplifier with merged n-inputs and a merged common-source with active load (MCSAL) circuit to choose the desired input. The advantages of the proposed structure are simplicity, very high resolution, very low supply voltage requirements, very low output resistor, low power dissipation, low active area and simple expansion for multiple inputs by adding only three transistors for each extra input. The post-layout simulation results of proposed circuits are presented by HSPICE software in 0.35-μm CMOS process technology. The total power dissipation of proposed circuits is about 110-μW. Also, the total active area is about 550-μm2 for five-input proposed circuits, and would be negligibly increased for each extra input.

IMPROVED DYNAMIC CURRENT MODE LOGIC FOR LOW POWER APPLICATIONS

2008 ◽  
Vol 17 (02) ◽  
pp. 183-190 ◽  
Author(s):  
S. RAMAKRISHNAN ◽  
K. T. LAU
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
Power Dissipation ◽  
Current Mode ◽  
Total Power ◽  
Active Mode ◽  
Dynamic Power ◽  
Current Mode Logic ◽  
Low Power Dissipation ◽  
Standby Mode

In this paper, a newly improved dynamic current mode logic (I-DyCML) is proposed to achieve low power dissipation. The principle used in I-DyCML is the reduction of the leakage current by turning the part of the circuit to "standby mode", when not in use, while achieving lower dynamic power during the active mode. HSpice simulations show that I-DyCML saves up to 15–30% of the total power dissipation when compared to Dynamic Current mode logic.

scholarly journals A 1.2 V, 8-bit, 100 MHz pipelined analog-to-digital converter

2021 ◽  
Author(s):  
Shahab Ardalan
Keyword(s):  
Power Dissipation ◽  
Low Voltage ◽  
Low Power Design ◽  
Cmos Technology ◽  
Total Power ◽  
Cable Modem ◽  
Analog To Digital Converter ◽  
Flat Panel Display ◽  
Digital Converter ◽  
Analog To Digital

A 1.2 V, 8 bit, 100 MSample/Sec Pipeline Analog-to-Digital Converter is designed in 0.18-μm standard CMOS technology. An emphasis was placed on observing the low voltage and low power design. The architecture of this ADC is 1 bit/stage pipelined configuration. With above specifications the designed ADC can be applicable for DVI flat-panel display; Giga bit Ethernet on copper, RGB to LCD converter and cable modem. This designed ADC can achieve SNDR 56dB in 100 MHz sampling frequency with 8 bit resolution. Total power dissipation is 40.6mW and INL is around 1 LSB and the maximum swing of the input is 1 Volt peak to peak which is almost rail-to-rail situation. The core area of the ADC excluding pads is around 0.25mm 2 .

scholarly journals TIQ Flash ADC Design using a Low Power Multiplier Based Encoder

2019 ◽  
Vol 8 (2S2) ◽  
pp. 226-229
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Power Supply Voltage ◽  
Large Power ◽  
Flash Adc ◽  
Analog To Digital ◽  
Tiq Comparator ◽  
The Impact

Threshold Inverter Quantization (TIQ) for applications of system-on-chip (SoC) depending on CMOS flash analog-to-digital converter (ADC). The TIQ technique which uses two cascaded CMOS inverters as a voltage comparator. However, this TIQ method must be created to meet the latest SoC trends, which force ADCs to be integrated with another electronic circuit on the chip and focus on low-power and low-voltage applications. TIQ comparator reduced the impact of variations in the process, temperature, and power supply voltage. Therefore, we obtained a higher TIQ flash ADC speed and resolution. TIQ flash ADC reduced / managed power dissipation. We obtain large power savings by managing the power dissipation in the comparator. Furthermore, the new comparator has a huge benefit in power dissipation and noise rejection comparative to the TIQ comparator [1]. The findings indicate that the TIQ flash ADC based on Modied mux attain heavy-speed transformation and has a tiny size, low-power dissipation and operation of lowvoltage compared to another flash ADCs.

scholarly journals DESIGN APPROACHES FOR LOW POWER- LOW AREA D FLIP FLOP S IN NANO TECHNOLOGY

2013 ◽  
pp. 231-236
Author(s):  
FAYAZ KHAN ◽  
SIREESH BABU
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Vital Role ◽  
Leakage Power ◽  
Total Power ◽  
Short Channel ◽  
Qualitative Comparison ◽  
Flip Flop ◽  
Low Area ◽  
Total Power Consumption

This paper enumerates design of D flip flop with low power and low area for low power applications, for that analysis of various D-flip flops for low power dissipation ,area and delays is carried out at 0.12um to achieve low power, low-area the technology is scaled down to nanometer ranges, due to shrinking process, the leakage power tends to play a vital role in total power consumption at nano meter technology. In this paper, different D flip flop circuits are designed using Berkeley Short Channel Insulated Gate MOSFET (BSIM4) model equations., in this paper to reduce leakage power at 90nm 70nm and 50nm we implement leakage power reduction techniques six techniques are considered they are namely Sleep transistor, sleepy stack, Dual sleep ,Dual stack Forced Transistor sleep (FTS) and Sleepy keeper From the results, it is observed that SLEEP TRANSISTOR, and SLEEPY KEEPER.FORCED TRANSISTOR SLEEP techniques produces lower power dissipation than the other techniques , in this paper a qualitative comparison is done with the help of Dsch,, Micro wind Simulation tools, this paper concludes that a leakage reduction technique produce different power optimization levels for different architectures and employing a suitable technique for a particular architecture will be an effective way of reducing the leakage current and thereby static power.

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