scholarly journals 50 MHz–10 GHz Low-Power Resistive Feedback Current-Reuse Mixer with Inductive Peaking for Cognitive Radio Receiver

2014 ◽  
Vol 2014 ◽  
pp. 1-11 ◽  
Author(s):  
Nandini Vitee ◽  
Harikrishnan Ramiah ◽  
Wei-Keat Chong ◽  
Gim-Heng Tan ◽  
Jeevan Kanesan ◽  
...  
Keyword(s):  
Cognitive Radio ◽  
Power Consumption ◽  
Low Power ◽  
Noise Figure ◽  
Cmos Technology ◽  
Radio Receiver ◽  
Conversion Gain ◽  
Current Reuse ◽  
Inductive Peaking ◽  
Resistive Feedback

A low-power wideband mixer is designed and implemented in 0.13 µm standard CMOS technology based on resistive feedback current-reuse (RFCR) configuration for the application of cognitive radio receiver. The proposed RFCR architecture incorporates an inductive peaking technique to compensate for gain roll-off at high frequency while enhancing the bandwidth. A complementary current-reuse technique is used between transconductance and IF stages to boost the conversion gain without additional power consumption by reusing the DC bias current of the LO stage. This downconversion double-balanced mixer exhibits a high and flat conversion gain (CG) of 14.9 ± 1.4 dB and a noise figure (NF) better than 12.8 dB. The maximum input 1-dB compression point (P1dB) and maximum input third-order intercept point (IIP3) are −13.6 dBm and −4.5 dBm, respectively, over the desired frequency ranging from 50 MHz to 10 GHz. The proposed circuit operates down to a supply headroom of 1 V with a low-power consumption of 3.5 mW.

scholarly journals A 60 GHz fully differential LNA in 90 nm CMOS technology

2013 ◽  
Vol 6 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Andrea Malignaggi ◽  
Amin Hamidian ◽  
Georg Boeck
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Transmission Lines ◽  
Noise Figure ◽  
Design Procedure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
60 Ghz ◽  
Fully Differential

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.

Low Voltage Low Power Up-Conversion Mixer for Wireless Sensor Networks Node Application

2013 ◽  
Vol 760-762 ◽  
pp. 516-520
Author(s):  
Ge Sun ◽  
Zhi Qun Li ◽  
Chen Jian Wu ◽  
Meng Zhang ◽  
Jia Cao ◽  
...  
Keyword(s):  
Wireless Sensor Networks ◽  
Sensor Networks ◽  
Low Power ◽  
Low Voltage ◽  
Noise Figure ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Wireless Sensor ◽  
Operating Voltage ◽  
Conversion Gain

A low voltage, low power up-conversion mixer is presented here for 2.4GHz wireless sensor networks (WSN). It was based on a double-balanced Gilbert cell type. The current-reuse technique was used to reduce the power consumption and negative-resistance compensation technique was used to improve the conversion gain. The mixer was designed in 0.18μm RF CMOS technology, and was simulated with Cadence SpectreRF. The simulation results indicate that the conversion gain is 6.37dB, the noise figure is 15.36dB and the input 1dB compression point is-10.3dBm, while consuming 1mA current for operating voltage at 1V.

Low-power CMOS LNA based on dual resistive-feedback structure with peaking inductor for wideband application

2013 ◽  
Vol 5 (1) ◽  
pp. 65-70 ◽  
Author(s):  
Meng-Ting Hsu ◽  
Shih-Yu Hsu ◽  
Yu-Hwa Lin
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Low Noise ◽  
Cmos Process ◽  
Output Stage ◽  
Chip Area ◽  
Inductive Peaking ◽  
Resistive Feedback ◽  
Low Power Cmos ◽  
Noise Amplifier

This paper presents a low-power and low-noise amplifier (LNA) with resistive-feedback configuration. The design consists of two resistive-feedback amplifiers. In order to reduce the chip area, a resistive-feedback inverter is adopted for input matching. The output stage adopts basic topology of an RC feedback for output matching, and adds two inductors for inductive peaking at the high band. The implemented LNA has a peak gain of 10.5 dB, the input reflection coefficient S11 is lower than −8 dB and the output reflection S22 is lower than −10.8 dB, and noise figure of 4.2–5.2 dB is between 1 and 10 GHz while consuming 12.65 mW from a 1.5 V supply. The chip area is only 0.69 mm2 and the figure of merit is 6.64 including the area estimation. The circuit was fabricated in a TSMC 0.18 um CMOS process.

scholarly journals Design of a very low-power, low-cost 60 GHz receiver front-end implemented in 65 nm CMOS technology

2011 ◽  
Vol 3 (2) ◽  
pp. 131-138 ◽  
Author(s):  
Michael Kraemer ◽  
Daniela Dragomirescu ◽  
Robert Plana
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Noise Figure ◽  
Low Cost ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Voltage Controlled Oscillator ◽  
60 Ghz ◽  
Front End

The research on the design of receiver front-ends for very high data-rate communication in the 60 GHz band in nanoscale Complementary Metal Oxide Semiconductor (CMOS) technologies is going on for some time now. Although a multitude of 60 GHz front-ends have been published in recent years, they are not consequently optimized for low power consumption. Thus, these front-ends dissipate too much power for battery-powered applications like handheld devices, mobile phones, and wireless sensor networks. This article describes the design of a direct conversion receiver front-end that addresses the issue of power consumption, while at the same time permitting low cost (due to area minimization by the use of spiral inductors). It is implemented in a 65 nm CMOS technology. The realized front-end achieves a record power consumption of only 43 mW including low-noise amplifier (LNA), mixer, a voltage controlled oscillator (VCO), a local oscillator (LO) buffer, and a baseband buffer (without this latter buffer the power consumption is even lower, only 29 mW). Its pad-limited size is 0.55 × 1 mm2. At the same time, the front-end achieves state-of-the-art performance with respect to its other properties: Its maximum measured power conversion gain is 30 dB, the RF and IF bandwidths are 56.5–61.5 and 0–1.5 GHz, respectively, its measured minimum noise figure is 9.2 dB, and its measured IP−1 dB is −36 dBm.

A Low-Power, High-Gain, and Low-Noise 802.11a Down-Conversion Mixer in 0.35-μm SiGe Bi-CMOS Technology

2017 ◽  
Vol 26 (09) ◽  
pp. 1750134 ◽  
Author(s):  
Jun-Da Chen ◽  
Song-Hao Wang
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Cmos Process ◽  
Conversion Gain ◽  
Dc Power ◽  
Down Conversion

The paper presents a novel 5.15[Formula: see text]GHz–5.825[Formula: see text]GHz SiGe Bi-CMOS down-conversion mixer for WLAN 802.11a receiver. The architecture used is based on Gilbert cell mixer, the combination of MOS transistors and HBT BJT transistor device characteristics. The hetero-junction bipolar transistor (HBT) topology is adopted at the transconductance stage to improve power gain and reduce noise factor, and the LO series-parallel CMOS switch topology will be applied to reduce supply voltage and dc power at the switching stage. This mixer is implemented in TSMC 0.35-[Formula: see text]m SiGe Bi-CMOS process, and the chip size including the test pads is 1.175*0.843[Formula: see text]mm2. The main advantages for the proposed mixer are high conversion gain, a moderate linearity, low noise figure, and low power. The post-simulation results achieved are as follows: 14[Formula: see text]dB power conversion gain, [Formula: see text]6[Formula: see text]dBm input third-order intercept point (IIP3), 6.85[Formula: see text]dB double side band (DSB) noise figure. The total mixer current is about 1.54[Formula: see text]mA from 1.4[Formula: see text]V supply voltage including output buffer. The total dc power consumption is 2.15[Formula: see text]mW.

A CMOS Low-Power Digital Variable Gain Amplifier Design for a Cognitive Radio Receiver “Application for IEEE 802.22 Standard”

2018 ◽  
Vol 27 (09) ◽  
pp. 1850135 ◽  
Author(s):  
Sawssen Lahiani ◽  
Samir Ben Salem ◽  
Houda Daoud ◽  
Mourad Loulou
Keyword(s):  
Cognitive Radio ◽  
Power Consumption ◽  
Low Power ◽  
High Gain ◽  
Low Noise ◽  
Constant Current ◽  
Variable Gain Amplifier ◽  
Low Power Consumption ◽  
Radio Receiver ◽  
Variable Gain

This paper presents the design of a new Digital Variable Gain Amplifier cell (DVGA). The proposed circuit based on transconductance, gm, amplifier and a transconductance amplifier is analyzed and designed for a cognitive radio receiver. The variable-gain amplifier (VGA) proposed consists of a digital control block, an auxiliary pair to retain a constant current density, and offers a gain-independent bandwidth (BW). A novel cell structure is designed for high gain, high BW, low power consumption and low Noise Figure (NF). The Heuristic Method is used to optimize the proposed circuit performance for high gain, low noise and low power consumption. This circuit is implemented and simulated using device-level description of TSMC 0.18[Formula: see text][Formula: see text]m CMOS process. Simulation results show that the DVGA can provide a gain variation range of 54[Formula: see text]dB (from 54[Formula: see text]dB to 0[Formula: see text]dB) with a 3[Formula: see text]dB BW over more than 110[Formula: see text]MHz. The circuit consumes the maximum power of 0.65[Formula: see text]mW from a 1.8[Formula: see text]V supply.

A 0.5–6.5-GHz 3.9-dB NF 7.2-mW active down-conversion mixer in 65-nm CMOS

2018 ◽  
Vol 32 (23) ◽  
pp. 1850278 ◽  
Author(s):  
Benqing Guo ◽  
Xuebing Wang ◽  
Hongpeng Chen ◽  
Jun Chen
Keyword(s):  
Power Consumption ◽  
Noise Figure ◽  
Cmos Process ◽  
Conversion Gain ◽  
Input Frequency ◽  
Frequency Range ◽  
Text Type ◽  
Current Reuse ◽  
Down Conversion ◽  
Noise Canceling

In the paper, a broadband CMOS active down-conversion mixer is presented. Specifically, a noise-canceling transconductor is developed to reduce the noise figure of the mixer. The current-reuse technique applied to the developed transconductor by stacked nMOS/pMOS architecture not only saves power consumption of the circuit, but also reduces the undesirable parasitics. Moreover, two passive [Formula: see text]-type networks are exploited to absorb internal parasitics of the circuit and guarantee broadband operation. Implemented in an advanced 65-nm CMOS process, post-simulations show that, driven by 0 dBm sinusoidal LO signal, the proposed mixer provides a maximal conversion gain of 15 dB and a NF of 3.9–4.9 dB across RF input frequency range of 0.5–6.5 GHz. The IIP3 and IP1dB of 3.1 and −6.9 dBm are obtained, respectively. The mixer core consumes 7.2 mW from a 1 V supply.

scholarly journals An Ultra-Low-Power K-Band 22.2 GHz-to-26.9 GHz Current-Reuse VCO Using Dynamic Back-Gate-Biasing Technique

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 889
Author(s):  
Xiaoying Deng ◽  
Peiqi Tan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Back Gate ◽  
Ultra Low Power ◽  
Current Reuse ◽  
K Band

An ultra-low-power K-band LC-VCO (voltage-controlled oscillator) with a wide tuning range is proposed in this paper. Based on the current-reuse topology, a dynamic back-gate-biasing technique is utilized to reduce power consumption and increase tuning range. With this technique, small dimension cross-coupled pairs are allowed, reducing parasitic capacitors and power consumption. Implemented in SMIC 55 nm 1P7M CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 22.2 GHz to 26.9 GHz, consuming only 1.9 mW–2.1 mW from 1.2 V supply and occupying a core area of 0.043 mm2. The phase noise ranges from −107.1 dBC/HZ to −101.9 dBc/Hz at 1 MHz offset over the whole tuning range, while the total harmonic distortion (THD) and output power achieve −40.6 dB and −2.9 dBm, respectively.

SECOND BIRTH OF TROPOSPHERIC COMMUNICATION. PHASED ANTENNA ARRAY COGNITIVE RADIO STATIONS

2020 ◽  
Author(s):  
Л.О. МЫРОВА ◽  
А.В. ШЕВЫРЕВ ◽  
С.А. МУСАЕЛЯН ◽  
И.С. ПОПОВ ◽  
В.А. ВОРОЩАК
Keyword(s):  
Cognitive Radio ◽  
Power Consumption ◽  
Low Power ◽  
Antenna Array ◽  
Radio Stations ◽  
Term Operation ◽  
Hardware Reliability ◽  
Phased Antenna Array ◽  
Technical Solutions

Рассмотрены новые прорывные технические решения по тропосферной связи на основе когнитивных радиостанций с фазированной антенной решеткой (ФАР). Показана возможность повышения (в десятки раз)аппаратурной надежности за счет исключения из состава ТРС мощных передатчиков и применения вместо них маломощных антенных приемопередающих модулей (АППМ),синфазноработающих в составе ФАР. Представлены преимуществами ТРС: возможность длительной работа без технического обслуживания, снижение вдвое энергопотребления, а также глубокая унификация построения ТРС разного класса на основе унифицированных АППМ. New breakthrough technical solutions for tropospheric communication based on cognitive radio stations with a phased antenna array (PAA) are considered. These solutions provide the possibility of increasing the hardware reliability tenfold due to exclusion of powerful transmitters from tropospheric stations (TS) and using instead of them low-power antenna receive-transmitting modules (ARTM), operating in phase as part of the PAA. The advantages of such TSs are shown that enable long-term operation without maintenance, halving power consumption, as well as deep unification of the construction of TSs of different classes based on unified ARTMs.

scholarly journals Design of Low Power UWB CMOS Low Noise Amplifier using Active Inductor for WLAN Receiver

2018 ◽  
Vol 7 (2.24) ◽  
pp. 448
Author(s):  
S Manjula ◽  
M Malleshwari ◽  
M Suganthy
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Wide Band ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Design System ◽  
Active Inductor ◽  
Chip Area ◽  
Noise Amplifier

This paper presents a low power Low Noise Amplifier (LNA) using 0.18µm CMOS technology for ultra wide band (UWB) applications. gm boosting common gate (CG) LNA is designed to improve the noise performance.  For the reduction of on chip area, active inductor is employed at the input side of the designed LNA for input impedance matching. The proposed UWB LNA is designed using Advanced Design System (ADS) at UWB frequency of 3.1-10.6 GHz. Simulation results show that the gain of 10.74+ 0.01 dB, noise figure is 4.855 dB, input return loss <-13 dB and 12.5 mW power consumption.  

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