scholarly journals Design of Low-Power Structural FIR Filter Using Data-Driven Clock Gating and Multibit Flip-Flops

2020 ◽  
Vol 2020 ◽  
pp. 1-9
Author(s):  
Lamjed Touil ◽  
Abdelaziz Hamdi ◽  
Ismail Gassoumi ◽  
Abdellatif Mtibaa
Keyword(s):  
Low Power ◽  
Power Saving ◽  
Digital Signal ◽  
Low Power Design ◽  
Fir Filter ◽  
Data Driven ◽  
Clock Gating ◽  
Consumption Reduction ◽  
Essential Components ◽  
Using Data

Optimization for power is one of the most important design objectives in modern digital signal processing (DSP) applications. The digital finite duration impulse response (FIR) filter is considered to be one of the most essential components of DSP, and consequently a number of extensive works had been carried out by researchers on the power optimization of the filters. Data-driven clock gating (DDCG) and multibit flip-flops (MBFFs) are two low-power design methods that are used and often treated separately. The combination of these methods into a single algorithm enables further power saving of the FIR filter. The experimental results show that the proposed FIR filter achieves 25% and 22% power consumption reduction compared to that using the conventional design.

scholarly journals A Low Power FIR Filter Design for Image Processing

VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 391-397 ◽  
Author(s):  
Jun Mo Jung ◽  
Jong-Wha Chong
Keyword(s):  
Image Processing ◽  
Low Power ◽  
Filter Design ◽  
Design Method ◽  
Low Power Design ◽  
Fir Filter ◽  
Correlated Data ◽  
Clock Signal ◽  
Clock Gating ◽  
Flip Flop

In this paper, a new low power design method of the FIR filter for image processing is proposed. Because the correlation between adjacent pixels is very high in image data, the clock gating technique can be a good candidate for low power strategy. However, the conventional clock gating strategy that is applied independently to every flip-flop of the filter give rise to too much additional area overhead and couldn't get a good result in the power reduction. In our method, each tap register, which is used to delay the input data in the filter, is partitioned into two sub-registers according to the correlation characteristic of its input space. For the sub-register which highly correlated data is inputted into, the dynamic power consumption is reduced by diminishing switching activity of the clock signal. We can also reduce the additional hardware overhead by propagating the clock gating control signal of the first tap register to other tap registers. To identify the efficiency of the proposed design method, we perform the experiments on some filters that are designed in VHDL. The power estimation tool says that the proposed method can reduce the power dissipation of the filter by more than 18% compared to the conventional filter design methods.

scholarly journals Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic

Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 243 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Douglas Maskell ◽  
Nikos Mastorakis
Keyword(s):  
Low Power ◽  
Digital Signal Processor ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Power Design ◽  
Cmos Technology ◽  
General Purpose ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Power Cycle

Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshaking. Many existing asynchronous ripple-carry adders (RCAs), carry lookahead adders (CLAs) and carry select adders (CSLAs) were implemented alongside to perform a comparison based on a 32/28 nm complementary metal-oxide-semiconductor (CMOS) technology. The 32-bit addition was considered for an example. For implementation using the delay-insensitive dual-rail code and subject to the 4-phase RTZ handshaking (4-phase RTO handshaking), the proposed BCLARC which is robust and of early output type achieves: (i) 8% (5.7%) reduction in PCTP compared to the optimum RCA, (ii) 14.9% (15.5%) reduction in PCTP compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum CSLA.

scholarly journals Low Power Design for ASIC Cores

VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 317-331
Author(s):  
Alvar Dean ◽  
David Garrett ◽  
Mircea R. Stan ◽  
Sebastian Ventrone
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Low Power Design ◽  
Clock Gating ◽  
Asic Design ◽  
Design Techniques

A semicustom ASIC design methodology is used to develop a low power DSP core for mobile (battery powered) applications. Different low power design techniques are used, including dual voltage, low power library elements, accurate power reporting, pseudomicrocode, transition-once logic, clock gating, and others.

Low Power Transposed Form 4-Tap Finite Impulse Response Filter using Power Efficient Multiply Accumulate Unit

2021 ◽  
pp. 2250016
Author(s):  
S. Rakesh ◽  
K. S. Vijula Grace
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
Speech Processing ◽  
Video Processing ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Low Power Design ◽  
Fir Filter ◽  
Efficient Design ◽  
Power Efficient

Finite impulse response (FIR) filters find wide application in signal processing applications on account of the stability and linear phase response of the filter. These digital filters are used in applications, like biomedical engineering, wireless communication, image processing, speech processing, digital audio and video processing. Low power design of FIR filter is one of the major constraints that researchers are trying hard to achieve. This paper presents the implementation of a novel power efficient design of a 4-tap 16-bit FIR filter using a modified Vedic multiplier (MVM) and a modified Han Carlson adder (MHCA). The units are coded using Verilog hardware description language and simulated using Xilinx Vivado Design Suite 2015.2. The filter is synthesized for the 7-series Artix field programmable gate array with xc7a100tcsg324-1 as the target device. The proposed filter design showed an improvement of a maximum of 57.44% and a minimum of 2.44% in the power consumption compared to the existing models.

Green Semicondoctor Design Techniques and Challanges

2011 ◽  
pp. 404-411
Author(s):  
Somesh Rajain ◽  
Chetan Shingala ◽  
Ekata Mehul
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Management ◽  
Human Life ◽  
Semiconductor Industry ◽  
Low Power Design ◽  
Clock Gating ◽  
Consumer Device ◽  
Carbon Dioxide Co2 ◽  
Design Techniques

The large emission of Carbon dioxide (CO2) is not only affecting our ecology but also affecting human life. In schools, offices, factory and crowded railway/bus stations i.e crowded places with insufficient ventilations CO2 affects human life most. In a closed environment like school, If CO2 level starts raising above 700 parts per million (ppm) people will feel objectionable body odors and as it increase further people will feel very uncomfortable, dizzy and have headache etc. Our goal is to reduce CO2 emission and lower global warming. In Semiconductor Industry as the digital technology grows, the functionality of our electronics devices (For example: - Mobile phone, PC’s, home appliances etc) is constantly improves and mean while the demand for electronic devices to be more environment friendly is increasing. So we have to design systems with Low power consumption to curtail down green house gas emission as well as low power design are also a requirement of today’s market. The usage of mobile device in all kinds of applications is increasing day by day. These applications and corresponding devices also have their power requirements. The demand for mobile consumer device has made the power management the number one consideration in today‘s system design. To increase battery life, system chip designer needs to adopt an aggressive power management technique which includes multi voltage Design Island, power gating, dynamic voltage, frequency scaling, clock gating etc in the system. Adding all these greatly complicates the verification for the chip. Normally the designer neglects the implementation of power saving techniques due to the tradeoff between power reduction and verification costs. The costs become more important in terms of business, which leads to more power consumption. Those details can still be implemented provided we use right kind of tools & techniques that are also combined with design experience. In this chapter the focus is to firstly describe low power design techniques, its verification challenges and its solutions followed by the case study. It also guides for the selection of programmable device & RTL Core design criteria. To make green electronics devices we have to design system with low power design techniques.

scholarly journals Power-Saving Design of Radio Frequency Identification Sensor Networks in Bus Seatbelt Monitoring Systems

Sensors ◽  
2020 ◽  
Vol 20 (20) ◽  
pp. 5882
Author(s):  
Sitong Sun ◽  
Wen Yang ◽  
Wilson Wang
Keyword(s):  
Sensor Networks ◽  
Low Power ◽  
Radio Frequency ◽  
Radio Frequency Identification ◽  
Power Saving ◽  
Low Power Design ◽  
Sensor Nodes ◽  
Design Approach ◽  
Registration Method ◽  
Frequency Identification

Seatbelt state monitoring is important in intercity buses for passenger safety. This paper discusses the issues and challenges in power-saving design of radio frequency identification (RFID) sensor networks in bus seatbelt monitoring. A new design approach is proposed in this work for low-power layout and parameter setting in RFID sensor nodes in hardware and software design. A one-to-many pairing registration method is suggested between the concentrator and the seat nodes. Unlike using extra computer software to write seat identification (ID) into an integrated circuit (IC) card, the node ID in this project can be stored into the concentrator directly, which can reduce intermediate operations and reduce development costs. The effectiveness of the proposed low-power design approach is verified by some experimental tests.

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