A Unified Approach for Performance Degradation Analysis from Transistor to Gate Level

2018 ◽  
Vol 8 (1) ◽  
pp. 412
Author(s):  
Izhar Hussain ◽  
Marco Vacca ◽  
Fabrizio Riente ◽  
Mariagrazia Graziano
Keyword(s):  
Oxide Thickness ◽  
Performance Degradation ◽  
Silicon On Insulator ◽  
Unified Approach ◽  
Hot Carrier ◽  
Random Dopant Fluctuation ◽  
Key Points ◽  
Degradation Analysis ◽  
Physical Effects ◽  
Technology Nodes

In this paper, we present an extensive analysis of the performance degradation in MOSFET based circuits. The physical effects that we consider are the random dopant fluctuation (RDF), the oxide thickness fluctuation (OTF) and the Hot-carrier-Instability (HCI). The work that we propose is based on two main key points: First, the performance degradation is studied considering BULK, Silicon-On-Insulator (SOI) and Double Gate (DG) MOSFET technologies. The analysis considers technology nodes from 45nm to 11nm. For the HCI effect we consider also the time-dependent evolution of the parameters of the circuit. Second, the analysis is performed from transistor level to gate level. Models are used to evaluate the variation of transistors key parameters, and how these variation affects performance at gate level as well.The work here presented was obtained using TAMTAMS Web, an open and publicly available framework for analysis of circuits based on transistors. The use of TAMTAMS Web greatly increases the value of this work, given that the analysis can be easily extended and improved in both complexity and depth.

Effect of B dose and Ge preamorphization energy on the electrical and structural properties of ultrashallow junctions in silicon-on-insulator

2006 ◽  
Vol 912 ◽  
Author(s):  
Justin J Hamilton ◽  
Erik JH Collart ◽  
Benjamin Colombeau ◽  
Massimo Bersani ◽  
Damiano Giubertoni ◽  
...  
Keyword(s):  
Structural Properties ◽  
Solid Phase ◽  
Silicon Film ◽  
Silicon On Insulator ◽  
Bulk Silicon ◽  
Defect Band ◽  
Future Technology ◽  
Ultrashallow Junctions ◽  
P Type ◽  
Technology Nodes

AbstractFormation of highly activated, ultra-shallow and abrupt profiles is a key requirement for the next generations of CMOS devices, particularly for source-drain extensions. For p-type dopant implants (boron), a promising method of increasing junction abruptness is to use Ge preamorphizing implants prior to ultra-low energy B implantation and solid-phase epitaxy regrowth to re-crystallize the amorphous Si. However, for future technology nodes, new issues arise when bulk silicon is supplanted by silicon-on-insulator (SOI). Previous results have shown that the buried Si/SiO2 interface can improve dopant activation, but the effect depends on the detailed preamorphization conditions and further optimization is required. In this paper a range of B doses and Ge energies have been chosen in order to situate the end-of-range (EOR) defect band at various distances from the back interface of the active silicon film (the interface with the buried oxide), in order to explore and optimize further the effect of the interface on dopant behavior. Electrical and structural properties were measured by Hall Effect and SIMS techniques. The results show that the boron deactivates less in SOI material than in bulk silicon, and crucially, that the effect increases as the distance from the EOR defect band to the back interface is decreased. For the closest distances, an increase in junction steepness is also observed, even though the B is located close to the top surface, and thus far from the back interface. The position of the EOR defect band shows the strongest influence for lower B doses.

Performance degradation analysis of solid lubricated bearings based on Laplace wavelet filter and self-organizing map

2013 ◽  
Vol 228 (10) ◽  
pp. 1743-1753 ◽  
Author(s):  
Chao Zhang ◽  
Shaoping Wang
Keyword(s):  
Feature Vector ◽  
Vibration Signal ◽  
Degradation Process ◽  
Performance Degradation ◽  
Friction Torque ◽  
Self Organizing Map ◽  
Wavelet Filter ◽  
Degradation Analysis ◽  
Space Mechanisms ◽  
Self Organizing

Solid lubricated bearings are commonly used in space mechanisms and other appliances, and their reliability analysis has drawn more and more attention. This paper focuses on the performance degradation analysis of solid lubricated bearings. Based on the vibration and friction torque signal of solid lubricated bearings, Laplace wavelet filter is adopted to process vibration signal and feature vector is constructed by calculating time-domain parameters of filtered vibration signal and original friction torque signal. Self-organizing map is then adopted to analyze the performance degradation based on extracted feature vectors. Experimental results show that this method can describe performance degradation process effectively.

High Temperature Reliability Investigations up to 350 °C of Gate Oxide Capacitors realized in a Silicon-on-Insulator CMOS-Technology

2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000116-000121
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
H. Vogt ◽  
U. Paschen
Keyword(s):  
High Temperature ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Single Poly Eeprom

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. With Silicon-on-Insulator-technologies (SOI), digital and analog circuitry is possible up to 250 °C and even more, but performance and reliability are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350 °C. The experiments were carried out on gate oxide capacitor structures which were realized in the Fraunhofer 1.0 μm SOI-CMOS process. This technology is based on 200 mm wafers and features, among others, three layers of tungsten metallization with excellent reliability concerning electromigration, voltage independent capacitors, high resistance resistors, and single-poly-EEPROM cells. The gate oxide thickness is 40 nm. Using the data of the TDDB-measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350 °C was evaluated. For a more detailed investigation, the current evolution in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250 °C, and make it possible to quickly evaluate the reliability of high temperature CMOS-technologies at use-temperature.

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