scholarly journals A New 8T SRAM Circuit with Low Leakage and High Data Stability Idle Mode at 70nm Technology

2017 ◽  
Vol 10 (1) ◽  
pp. 86-93 ◽  
Author(s):  
P Raikwal ◽  
V Neema ◽  
A Verma
Keyword(s):  
Leakage Current ◽  
Threshold Voltage ◽  
High Threshold ◽  
Idle Mode ◽  
High Data ◽  
Low Leakage ◽  
Noise Margin ◽  
Threshold Voltages ◽  
Sram Cell ◽  
Low Threshold

Memory has been facing several problems in which the leakage current is the most severe. Many techniques have been proposed to withstand leakage control such as power gating and ground gating. In this paper a new 8T SRAM cell, which adopts a single bit line scheme has been proposed to limit the leakage current as well as to gain high hold static noise margin. The proposed cell with low threshold voltage, high threshold voltage and dual threshold voltage are used to effectively reduce leakage current, and delay. Additionally, the comparison has been performed between conventional 6T SRAM cell and the new 8T SRAM cell. The proposed circuit consumes 671.22 pA leakage current during idle state of the circuit which is very less as compare to conventional 6T SRAM cell with sleep and hold transistors and with different β ratio. The proposed new 8T SRAM cell shows highest noise immunity 0.329mv during hold state. Furthermore, the proposed new 8T SRAM circuit represents minimum read and write access delays 114.13ps and 38.56ps respectively as compare to conventional 6T SRAM cell with different threshold voltages and β ratio.

1200-V JBS Diodes with Low Threshold Voltage and Low Leakage Current

2008 ◽  
Vol 600-603 ◽  
pp. 939-942 ◽  
Author(s):  
Takeo Yamamoto ◽  
Jun Kojima ◽  
Takeshi Endo ◽  
Eiichi Okuno ◽  
Toshio Sakakibara ◽  
...  
Keyword(s):  
Leakage Current ◽  
Schottky Diode ◽  
Threshold Voltage ◽  
Reverse Bias ◽  
Electrical Characteristics ◽  
Low Leakage ◽  
Forward Current ◽  
Low Leakage Current ◽  
Low Threshold ◽  
Power Application

4H-SiC SBDs have been developed by many researchers and commercialized for power application devices in recent years. At present time, the issues of an SiC-SBD are lower on-state current and a relatively larger-leakage current at the reverse bias than Si-PN diodes. A JBS (Junction Barrier Schottky) diode was proposed as a structure to realize a lower leakage current. We simulated the electrical characteristics of JBS diodes, where the Schottky electrode was made of molybdenum in order to optimize its performance. We fabricated JBS diodes based on the simulation with a diameter of 3.9mm (11.9 mm2). The JBS diode has a lower threshold voltage of 0.45 V, a large forward current of 40 A at Vf = 2.5V and a high breakdown voltage of 1660 V. Furthermore, the leakage current at 1200 V was remarkably low (Ir = 20 nA).

LOW-LEAKAGE FLIP-FLOPS BASED ON DUAL-THRESHOLD AND MULTIPLE LEAKAGE REDUCTION TECHNIQUES

2011 ◽  
Vol 20 (01) ◽  
pp. 147-162 ◽  
Author(s):  
WEIQIANG ZHANG ◽  
LI SU ◽  
YU ZHANG ◽  
LINFENG LI ◽  
JIANPING HU
Keyword(s):  
Total Power ◽  
High Threshold ◽  
Leakage Currents ◽  
Flip Flop ◽  
Leakage Reduction ◽  
Low Leakage ◽  
Reduction Techniques ◽  
Low Threshold ◽  
Critical Paths ◽  
P Type

The scaling of transistor sizes has resulted in dramatic increase of leakage currents. The sub-threshold and gate leakages have now become a major contributor to total power dissipations. This paper presents two flip-flops based on dual-threshold CMOS and multiple leakage reduction techniques to reduce their leakage dissipations. In the DT-TG FF (Dual-Threshold Transmission Gate Flip-Flop), some transistors on non-critical paths use high-threshold devices to reduce their leakage currents, while the other transistors on critical paths use low-threshold devices to maintain performance. The MLRT FF (Multiple Leakage Reduction Technique Flip-Flop) uses P-type CMOS techniques, MTCMOS (Multi-Threshold CMOS) power-gating and dual-threshold technique to reduce both sub-threshold and gate leakage dissipations. Taken as an example, a practical sequential system realized with the two low-leakage flip-flops is demonstrated using a mode-5 × 5 × 5 counter. The simulation results show that the two flip-flops achieve considerable leakage reductions.

scholarly journals A Novel Design of Low-Power 1-Bit CMOS Full-Adder Cell using XNOR and MUX

2013 ◽  
Vol 7 (3) ◽  
pp. 1155-1165
Author(s):  
Dayadi Lakshmaiah ◽  
Dr. M.V. Subramanyam ◽  
Dr. K.Sathya Prasad
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
Supply Voltage ◽  
Full Adder ◽  
High Threshold ◽  
Low Threshold ◽  
Supply Voltage Scaling ◽  
Critical Paths ◽  
Power Delay Product ◽  
Novel Design

This paper process a novel design for low power 1-bit CMOS full adder using XNOR and MUX, with reduced number of transistors using GDI cell. The circuits were simulated with supply voltage scaling from 1.2V to 0.6V &0.6V to 0.3V. To achieve the desired performance of power delay product, area, capacitance the transistors with low threshold voltage were used at critical paths and high threshold voltage at non critical paths. The results show the efficiency of the proposed technique in terms of power consumption, delay and area.

Area postrema voltage-activated calcium currents

1996 ◽  
Vol 75 (1) ◽  
pp. 133-141 ◽  
Author(s):  
M. Hay ◽  
E. M. Hasser ◽  
K. A. Lindsley
Keyword(s):  
Threshold Voltage ◽  
Area Postrema ◽  
Threshold Current ◽  
Calcium Currents ◽  
High Threshold ◽  
Patch Clamp Technique ◽  
Experimental Conditions ◽  
Nickel Ions ◽  
Transient Component ◽  
Low Threshold

1. Calcium currents in rabbit area postrema neurons were studied with the perforated patch-clamp technique. Experimental conditions eliminated Na+ and K+ currents and identified both low- and high-threshold voltage-activated calcium currents. 2. Low-threshold, T-type calcium currents were observed in 64% of the area postrema neurons recorded. This current activated near -60 mV and had an average peak amplitude of -36.2 +/- 5 pA (mean +/- SE) at -40 mV. This current began rapid inactivation near -95 mV, reached half-maximal inactivation at -71 mV and was totally inactivated by -40 mV. 3. A high-threshold transient current was recorded in all area postrema neurons, which consisted of both a transient and sustained component. This current was present at voltages greater than -40 mV and the transient component of this current was responsible for the majority of the total Ca2+ current. 4. Nickel ions (10 microM) effectively reduced both the T-type current and the high-threshold current. Cadmium ions (100 microM) effectively reduced the high-threshold current while having insignificant effects on the low-threshold current. 5. Application of the dihydropyridine antagonist nimodipine (1-10 microM) had no effect on either the low- or high-threshold voltage-activated calcium Ca2+ in area postrema neurons. In addition, application of omega-conotoxin-GVIA (2-10 microM) was also without effect on either the low- or high-threshold voltage-activated Ca2+ current, suggesting that area postrema neurons possess neither L- or N-type voltage-activated Ca2+ currents. 6. Application of omega-conotoxin MVIIC (10 microM) significantly inhibited the peak high-threshold Ca2+ current by 65.4% suggesting that area postrema neurons do possess a omega-conotoxin MVIIC-sensitive high-threshold Ca2+ channel. 7. Arg-vasopressin (150 nM) significantly increased the transient component of the high-threshold Ca2+ current but had little effect on either the low-threshold or the high-threshold sustained component.

Variability aware FinFET SRAM cell with improved stability and power for low power applications

Circuit World ◽  
2019 ◽  
Vol 45 (4) ◽  
pp. 196-207
Author(s):  
Shilpi Birla
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
Leakage Power ◽  
Static Noise Margin ◽  
Content Type ◽  
Noise Margin ◽  
Sram Cell ◽  
Memory Circuits ◽  
The Stability ◽  
Static Noise

Purpose Major area of a die is consumed in memory components. Almost 60-70% of chip area is being consumed by “Memory Circuits”. The dominant memory in this market is SRAM, even though the SRAM size is larger than embedded DRAM, as SRAM does not have yield issues and the cost is not high as compared to DRAM. At the same time, the other attractive feature for the SRAM is speed, and it can be used for low power applications. CMOS SRAM is the crucial component in microprocessor chips and applications, and as the said major portion of the area is dedicated to SRAM arrays, CMOS SRAM is considered to be the stack holders in the memory market. Because of the scaling feature of CMOS, SRAM had its hold in the market over the past few decades. In recent years, the limitations of the CMOS scaling have raised so many issues like short channel effects, threshold voltage variations. The increased thrust for alternative devices leads to FinFET. FinFET is emerging as one of the suitable alternatives for CMOS and in the region of memory circuits. Design/methodology/approach In this paper, a new 11 T SRAM cell using FinFET technology has been proposed, the basic component of the cell is the 6 T SRAM cell with 4 NMOS access transistors to improve the stability and also makes it a dual port memory cell. The proposed cell uses a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability thus, helps in reducing the leakage power and active power. Findings The cell shows improvement in RSNM (read static noise margin) with LP8T by 2.39× at sub-threshold voltage 2.68× with D6T SRAM cell, 5.5× with TG8T. The WSNM (write static noise margin) and HM (hold margin) of the SRAM cell at 0.9 V is 306 mV and 384  mV. It shows improvement at sub-threshold operation also. The leakage power is reduced by 0.125× with LP8T, 0.022× with D6T SRAM cell, TG8T and SE8T. The impact of process variation on cell stability is also discussed. Research limitations/implications The FinFet has been used in place of CMOS even though the FinFet has been not been a matured technology; therefore, pdk files have been used. Practical implications SRAM cell has been designed which has good stability and reduced leakage by which we can make an array and which can be used as SRAM array. Social implications The cell can be used for SRAM memory for low power consumptions. Originality/value The work has been done by implementing various leakage techniques to design a stable and improved SRAM cell. The advantage of this work is that the cell has been working for low voltage without degrading the stability factor.

scholarly journals Leakage Power Analysis of Domino XOR Gate

2013 ◽  
Vol 2013 ◽  
pp. 1-7 ◽  
Author(s):  
A. K. Pandey ◽  
R. A. Mishra ◽  
R. K. Nagaria
Keyword(s):  
Power Consumption ◽  
Threshold Voltage ◽  
Power Analysis ◽  
Leakage Power ◽  
Xor Gate ◽  
Active Mode ◽  
Hybrid Topology ◽  
Threshold Voltages ◽  
Low Threshold ◽  
Simulation Parameters

Two new XOR gates are proposed. First proposed circuits adopt hybrid transistor topology in the pull-down network with all transistors being low threshold voltages. A second proposed circuit adopts hybrid topology with dual threshold voltage transistors. Simulation parameters are measured at 25°C and 110°C. First proposed circuit reduces leakage power consumption up to 50% at 25°C and 58% at 110°C as compared to standard N-type domino XOR gate. It also reduces active mode power consumption by 14% as compared to standard N-type domino XOR gate. Similarly, second proposed circuit reduces leakage power consumption up to 73% at 25°C and 90% at 110°C as compared to standard N-type domino XOR gate. It also reduces active mode power consumption by 39% as compared to standard N-type domino XOR gate.

DUAL THRESHOLD VOLTAGE DOMINO ADDER DESIGN WITH PASS TRANSISTOR LOGIC USING STANDBY SWITCH FOR REDUCING SUB-THRESHOLD LEAKAGE CURRENT

2014 ◽  
Vol 23 (03) ◽  
pp. 1450043
Author(s):  
SHOUCAI YUAN ◽  
YAMEI LIU
Keyword(s):  
Integrated Circuits ◽  
Leakage Current ◽  
Threshold Voltage ◽  
Clock Cycle ◽  
Dynamic Logic ◽  
Cmos Technology ◽  
Propagation Delay ◽  
High Threshold ◽  
Pass Transistor ◽  
Dual Threshold Voltage

Standby switch can strongly turn off all the high threshold voltage transistors, which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce sub-threshold leakage current. Sub-threshold leakage currents are especially important in burst mode type integrated circuits where the system is in an idle mode in the majority of the time. The standby switch allows a domino system to enter and leave a low leakage standby mode within a single clock cycle. In addition, we combine domino dynamic logic with pass transistor XNOR and pass transistor NAND gates to achieve logic 1 output during its precharge phase without affecting circuits operation in its evaluation and standby phase. The required process for dual threshold voltage circuit configuration involves only one additional ion implant step to provide an extra threshold voltage. SPICE simulation for our proposed circuits is made using a 0.18 μm CMOS processes from TSMC, with 10 fF capacitive loads in all output nodes, and parameters for typical process corner at 25°C. Layout is designed, wafer is fabricate and measured. The measurement results of fabricated chips are listed and verify that our designed 8-bit carry look-ahead adders (CLAs) reduced power consumption and propagation delay time by more than 15% and around 20%, respectively, when compared with the prior work.

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