scholarly journals Failure Analysis at Stem Valve Fire Hydrant in LNG Plant

Author(s):  
JULI MRIHARDJONO ◽  
HERMAN ABIDIN POHAN ◽  
SENO DARMANTO

Hydrant is one of fire extinguisher fix system that use pressure water and flowed through the pipes and fire hose. There are more 250 Hydrant in this LNG Plant and based on finding at the field, many stem valve of outlet hydrant in fracture condition, therefore the author wants to analyze about the problem from this material, this reserch aims to find out root cause dan conduct failure analysis, method of reserch that conducted is visual check  to predict possible cause from failure of stem valve fire hydrant and then conducted fractographic analysis to find out what type of fracture that happen to this material and Tensile Strenght Test to Find out the the actual strenght of the material

Author(s):  
Yu Hsiang Shu ◽  
Vincent Huang ◽  
Chia Hsing Chao

Abstract Using nanoprobing techniques to accomplish transistor parametric data has been reported as a method of failure analysis in nanometer scale defect. In this paper, we focus on how to identify the influence of Contact high resistance on device soft failures using nanoprobing analysis, and showing that the equivalent mathematical models could be used to describe the corresponding electrical data in a device with Contact high resistance issue. A case study was presented to verify that Contact volcano defect caused Contact high resistance issue, and this issue can be identified via physical failure analysis (PFA) method (e.g. Transmission Electron Microscope and Focus Ion Beam techniques) and nanoprobing analysis method. Finally, we would explain the physical root cause of Contact volcano issue.


2021 ◽  
Vol 1043 (2) ◽  
pp. 022024
Author(s):  
Hongjian Wang ◽  
Zhenbo Zhao ◽  
Zongbei Dai ◽  
Zeya Peng ◽  
Shaoping Li

Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.


Author(s):  
E. Widener ◽  
S. Tatti ◽  
P. Schani ◽  
S. Crown ◽  
B. Dunnigan ◽  
...  

Abstract A new 0.5 um 1 Megabit SRAM which employed a double metal, triple poly CMOS process with Tungsten plug metal to poly /silicon contacts was introduced. During burn-in of this product, high currents, apparently due to electrical overstress, were experienced. Electrical analysis showed abnormal supply current characteristics at high voltages. Failure analysis identified the sites of the high currents of the bum-in rejects and discovered cracks in the glue layer prior to Tungsten deposition as the root cause of the failure. The glue layer cracks allowed a reaction with the poly/silicon, causing opens at the bottom of contacts. These floating nodes caused high currents and often latch-up during burn-in. Designed experiments in the wafer fab identified an improved glue layer process, which has been implemented. The new process shows improvement in burn in performance as well as outgoing product quality.


Author(s):  
Hashim Ismail ◽  
Ang Chung Keow ◽  
Kenny Gan Chye Siong

Abstract An output switching malfunction was reported on a bridge driver IC. The electrical verification testing revealed evidence of an earlier over current condition resulting from an abnormal voltage sense during a switching event. Based on these test results, we developed the hypothesis that a threshold voltage mismatch existed between the sense transistor and the output transistor. This paper describes the failure analysis approach we used to characterize the threshold voltage mismatch as well as our approach to determine the root cause, which was trapped charge on the gate oxide of the sense transistor.


Author(s):  
D. Zudhistira ◽  
V. Viswanathan ◽  
V. Narang ◽  
J.M. Chin ◽  
S. Sharang ◽  
...  

Abstract Deprocessing is an essential step in the physical failure analysis of ICs. Typically, this is accomplished by techniques such as wet chemical methods, RIE, and mechanical manual polishing. Manual polishing suffers from highly non-uniform delayering particularly for sub 20nm technologies due to aggressive back-end-of-line scaling and porous ultra low-k dielectric films. Recently gas assisted Xe plasma FIB has demonstrated uniform delayering of the metal and dielectric layers, achieving a planar surface of heterogeneous materials. In this paper, the successful application of this technique to delayer sub-20 nm microprocessor chips with real defects to root cause the failure is presented.


Author(s):  
Erik Paul ◽  
Holger Herzog ◽  
Sören Jansen ◽  
Christian Hobert ◽  
Eckhard Langer

Abstract This paper presents an effective device-level failure analysis (FA) method which uses a high-resolution low-kV Scanning Electron Microscope (SEM) in combination with an integrated state-of-the-art nanomanipulator to locate and characterize single defects in failing CMOS devices. The presented case studies utilize several FA-techniques in combination with SEM-based nanoprobing for nanometer node technologies and demonstrate how these methods are used to investigate the root cause of IC device failures. The methodology represents a highly-efficient physical failure analysis flow for 28nm and larger technology nodes.


Author(s):  
Keith Harber ◽  
Steve Brockett

Abstract This paper outlines the failure analysis of a Radio Frequency only (RF-only) failure on a complex Multimode Multiband Power Amplifier (MMPA) module, where slightly lower gain was observed in one mode of operation. 2 port S-parameter information was collected and utilized to help localize the circuitry causing the issue. A slight DC electrical difference was observed, and simulation was utilized to confirm that difference was causing the observed S-parameters. Physical analysis uncovered a very visible cause for the RF-only failure.


Author(s):  
Nathan Wang ◽  
Saunil Shah ◽  
Camille Garcia ◽  
Vicente Pasating ◽  
George Perreault

Abstract MEMS samples, with their relatively large size and weight, present a unique challenge to the failure analyst as they also included thin films and microstructures used in conventional integrated circuits. This paper describes how to accommodate the large MEMS structures without skimping on the microanalyses needed to get to the root cause. Investigations of tuning folk gyroscopes were used to demonstrate these new techniques.


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