Effect of dopant (Nb) concentration on the grain boundary electrical properties of Nb-doped barium titanate

2003 ◽  
Vol 18 (1) ◽  
pp. 88-96 ◽  
Author(s):  
Seok-Hyun Yoon ◽  
Hwan Kim
Keyword(s):  
Electrical Properties ◽  
Grain Boundary ◽  
Grain Boundaries ◽  
Energy Levels ◽  
Defect Mode ◽  
Impedance Analysis ◽  
Interface State ◽  
Oxygen Adsorption ◽  
State Density ◽  
Coarse Grained

A series of coarse-grained BaTiO3 specimens with different dopant (Nb) concentrations were prepared by adjusting the oxygen partial pressure during sintering. They were again heat-treated in air, and the behavior of the grain boundary electrical properties with the increase of Nb concentration was investigated under the conditions of the same microstructure and heat treatment. The interface states of the grain boundaries were estimated using the grain boundary R (resistance) and C (capacitance) values at each temperature that were obtained from impedance analysis. An increase in the interface state density at certain energy levels with increasing Nb concentration was verified experimentally. One type of interface state was observed for specimens with low Nb concentrations and another for specimens with high Nb concentrations. It is proposed that the changes in the interface state with increasing Nb concentration are related to the transition of the compensating defect mode and differences in the extent of oxygen adsorption at the grain boundaries.

Grain Boundary Defects Induced Switching in Zn- Bi- Mo Ceramic

2006 ◽  
Vol 251-252 ◽  
pp. 13-20 ◽  
Author(s):  
M. El-Hofy
Keyword(s):  
Grain Boundary ◽  
Grain Boundaries ◽  
Interface State ◽  
State Density ◽  
Switching Voltage ◽  
X Ray Diffraction ◽  
Minor Phase ◽  
Interface Potential ◽  
Two Phases ◽  
A Minor

Three Zinc Molybdenum ceramic samples doped Bi have been prepared according to the chemical formula (1-x) ZnO – 0.2MoO3 – xBi2O3, where (x = 0.2, 0.5, 1.0) mol %. The samples were studied at room temperature through X-ray Diffraction analysis, SEM, EDAX, I-V characteristics and C-V measurements. The results decleared the presences of two phases; ZnO as a major phase beside Bi2MoO6 as a minor phase. At lower Bi additions; Bi and Mo ions are highly segregated at the grain boundaries, while at higher additions more homogenous distribution for these ions inside the grain is observed. Some pores are observed around the batches of the minor phase and at the grain boundaries. The grain size is enlarged with increasing Bi addition; while the number and size of the pores are decrease. Creation of the pores is attributed to oxygen liberation from the surface of the sample during sintering. Formation of Schottky barrier is indicated via I-V and C-V measurements and attributed to Zn vacancies at the grain boundary. Interface potential barrier, donor density, interface state density and barrier width are decrease with increasing Bi addition. I-V characteristics revealed voltage switching. The switching voltage E0 decreases with increasing Bi addition and it is reproducible even after several on-off cycles.

Impact of a Treatment Combining Nitrogen Plasma Exposure and Forming Gas Annealing on Defect Passivation of SiO2/SiC Interfaces

2009 ◽  
Vol 615-617 ◽  
pp. 525-528 ◽  
Author(s):  
Heiji Watanabe ◽  
Yuu Watanabe ◽  
Makoto Harada ◽  
Yusuke Kagei ◽  
Takashi Kirino ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Energy Levels ◽  
Interface State ◽  
Nitrogen Plasma ◽  
State Density ◽  
Carbon Clusters ◽  
Plasma Exposure ◽  
Fixed Charges ◽  
Mos Devices ◽  
Defect Passivation

We propose a treatment combining nitrogen plasma exposure and forming gas annealing (FGA) to improve the electrical properties of SiO2/SiC interfaces. Although conventional FGA at 450°C alone is not effective for reducing interface traps and fixed charges, our combination treatment effectively reduces both even at moderate temperatures. We achieved further improvement by applying our treatment at higher (over 900°C) FGA temperatures, including lower interface state density (Dit) values for both deep and shallow energy levels (1 - 4 x 1011 cm-2eV-1). Considering that nitrogen incorporation promotes hydrogen passivation of interface defects, a possible mechanism for the improved electrical properties is that interface nitridation eliminates carbon clusters or Si-O-C bonds, which leads to the formation of simple Si and C dangling bonds that can be readily terminated by hydrogen. We therefore believe that our treatment is a promising method for improving the performance of SiC-based MOS devices.

scholarly journals Effects of Charge Compensation on Colossal Permittivity and Electrical Properties of Grain Boundary of CaCu3Ti4O12 Ceramics Substituted by Al3+ and Ta5+/Nb5+

Molecules ◽  
2021 ◽  
Vol 26 (11) ◽  
pp. 3294
Author(s):  
Jakkree Boonlakhorn ◽  
Jedsada Manyam ◽  
Pornjuk Srepusharawoot ◽  
Sriprajak Krongsuk ◽  
Prasit Thongbai
Keyword(s):  
Dielectric Properties ◽  
Electrical Properties ◽  
Grain Boundary ◽  
Grain Boundaries ◽  
Barrier Height ◽  
Potential Barrier ◽  
Charge Compensation ◽  
Solid State Reaction Method ◽  
Wide Frequency Range ◽  
Potential Barrier Height

The effects of charge compensation on dielectric and electrical properties of CaCu3Ti4-x(Al1/2Ta1/4Nb1/4)xO12 ceramics (x = 0−0.05) prepared by a solid-state reaction method were studied based on the configuration of defect dipoles. A single phase of CaCu3Ti4O12 was observed in all ceramics with a slight change in lattice parameters. The mean grain size of CaCu3Ti4-x(Al1/2Ta1/4Nb1/4)xO12 ceramics was slightly smaller than that of the undoped ceramic. The dielectric loss tangent can be reduced by a factor of 13 (tanδ ~0.017), while the dielectric permittivity was higher than 104 over a wide frequency range. Impedance spectroscopy showed that the significant decrease in tanδ was attributed to the highly increased resistance of the grain boundary by two orders of magnitude. The DFT calculation showed that the preferential sites of Al and Nb/Ta were closed together in the Ti sites, forming self-charge compensation, and resulting in the enhanced potential barrier height at the grain boundary. Therefore, the improved dielectric properties of CaCu3Ti4-x(Al1/2Ta1/4Nb1/4)xO12 ceramics associated with the enhanced electrical properties of grain boundaries. In addition, the non-Ohmic properties were also improved. Characterization of the grain boundaries under a DC bias showed the reduction of potential barrier height at the grain boundary. The overall results indicated that the origin of the colossal dielectric properties was caused by the internal barrier layer capacitor structure, in which the Schottky barriers at the grain boundaries were formed.

Properties of Thin SiO2 Films with In-Situ Deposition of Poly Si Electrodes

1989 ◽  
Vol 146 ◽  
Author(s):  
Paihung Pan ◽  
Ahmad Kermani ◽  
Wayne Berry ◽  
Jimmy Liao
Keyword(s):  
Electrical Properties ◽  
Breakdown Strength ◽  
Chemical Vapor ◽  
Interface State ◽  
State Density ◽  
In Situ Deposition ◽  
Different Temperatures ◽  
Flatband Voltage ◽  
Si Films

ABSTRACTElectrical properties of thin (12 nm) SiO2 films with and without in-situ deposited poly Si electrodes have been studied. Thin SiO2 films were grown by the rapid thermal oxidation (RTO) process and the poly Si films were deposited by the rapid thermal chemical vapor deposition (RTCVD) technique at 675°C and 800°C. Good electrical properties were observed for SiO2 films with thin in-situ poly Si deposition; the flatband voltage was ∼ -0.86 V, the interface state density was < 2 × 1010/cm2/eV, and breakdown strength was > 10 MV/cm. The properties of RTCVD poly Si were also studied. The grain size was 10-60 rim before anneal and was 50-120 rim after anneal. Voids were found in thin (< 70 nm) RTCVD poly Si films. No difference in either SiO2 properties or poly Si properties was observed for poly Si films deposited at different temperatures.

Processing and Characterization of MOS Capacitors Fabricated on 2°-Off Axis 4H-SiC Epilayers

2016 ◽  
Vol 858 ◽  
pp. 663-666
Author(s):  
Marilena Vivona ◽  
Patrick Fiorenza ◽  
Tomasz Sledziewski ◽  
Alexandra Gkanatsiou ◽  
Michael Krieger ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Interface State ◽  
State Density ◽  
Metal Oxide Semiconductor ◽  
Interface State Density ◽  
Device Fabrication ◽  
Oxide Semiconductor ◽  
Mos Capacitors ◽  
Oxide Breakdown

In this work, the electrical properties of SiO2/SiC interfaces onto a 2°-off axis 4H-SiC layer were studied and validated through the processing and characterization of metal-oxide-semiconductor (MOS) capacitors. The electrical analyses on the MOS capacitors gave an interface state density in the low 1×1012 eV-1cm-2 range, which results comparable to the standard 4°-off-axis 4H-SiC, currently used for device fabrication. From Fowler-Nordheim analysis and breakdown measurements, a barrier height of 2.9 eV and an oxide breakdown of 10.3 MV/cm were determined. The results demonstrate the maturity of the 2°-off axis material and pave the way for the fabrication of 4H-SiC MOSFET devices on this misorientation angle.

Structure and Surface Morphology of Thermal SiO2 Grown on 4H-SiC by Metal-Enhanced Oxidation Using Barium

2017 ◽  
Vol 897 ◽  
pp. 340-343 ◽  
Author(s):  
Atthawut Chanthaphan ◽  
Yoshihito Katsu ◽  
Takuji Hosoi ◽  
Takayoshi Shimura ◽  
Heiji Watanabe
Keyword(s):  
Electrical Properties ◽  
Surface Morphology ◽  
Silicon Dioxide ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Surface Roughening ◽  
Oxide Surface ◽  
Capping Layer ◽  
Enhanced Oxidation

Surface morphology and electrical properties of silicon dioxide (SiO2) on 4H-SiC substrates formed by metal-enhanced oxidation (MEO) using barium (Ba) atoms were systematically investigated. It was found that severe surface roughening caused by Ba-MEO can be suppressed by using SiO2 capping prior to MEO. The Ba atoms at the SiO2/SiC interface were found to diffuse to the oxide surface through the deposited SiO2 capping layer, and then the Ba density reduced to ~1014 cm-2 before stable MEO. The resulting SiO2/SiC interface showed the reduced interface state density but the insulating property of the oxides was significantly degraded.

Nanocrystalline Diamond as a Dielectric for SOD Applications

2007 ◽  
Vol 1039 ◽  
Author(s):  
Mose Bevilacqua ◽  
Niall Tumilty ◽  
Aysha Chaudhary ◽  
Haitao Ye ◽  
James E Butler ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Grain Boundary ◽  
Grain Boundaries ◽  
Microwave Plasma ◽  
Chemical Vapour ◽  
Polycrystalline Diamond ◽  
Growth Conditions ◽  
Nanocrystalline Diamond ◽  
Free Standing ◽  
Single Crystal Diamond

AbstractNanocrystalline diamond (NCD) has been grown on oxide coated silicon wafers by microwave plasma assisted chemical vapour deposition using a novel seeding technique followed by optimised growth conditions, and leads to a highly-dense form of this material with grain sizes around 100nm for films approximately 1.5 microns thick. The electrical properties of these films have been investigated using Impedance Spectroscopy, which enables the contributions from sources characterised by differing capacitances, such as grain boundaries and grain interiors, to be isolated. After an initial acid clean the electrical properties of the film are not stable, and both grain boundaries and grains themselves contribute to the frequency dependant impedance values recorded. However, following mild oxidation grain boundary conduction is completely removed and the films become highly resistive (>1013 ohm/sq). This is most unusual, as conduction through NCD material is more normally dominated by grain boundary effects. Interestingly, the AC properties of these films are also excellent with a dielectric loss value (tan δ) as low as 0.002 for frequencies up to 10MHz. The dielectric properties of these NCD films are therefore as good as high quality free-standing (large grain) polycrystalline diamond films, and not too dissimilar to single crystal diamond, and are therefore ideally suited to future ‘silicon-on-diamond’ applications.

Novel Approach for Improving Interface Quality of 4H-SiC MOS Devices with UV Irradiation and Subsequent Thermal Annealing

2013 ◽  
Vol 740-742 ◽  
pp. 741-744 ◽  
Author(s):  
Heiji Watanabe ◽  
Daisuke Ikeguchi ◽  
Takashi Kirino ◽  
Shuhei Mitani ◽  
Yuki Nakano ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Thermal Annealing ◽  
Uv Irradiation ◽  
Uv Light ◽  
Interface State ◽  
State Density ◽  
Mos Devices ◽  
Novel Approach ◽  
Subsequent Thermal Annealing ◽  
Thermally Grown

We report on the harmful impact of ultraviolet (UV) light irradiation on thermally grown SiO2/4H-SiC(0001) structures and its use in subsequent thermal annealing for improving electrical properties of SiC-MOS devices. As we previously reported [1], significant UV-induced damage, such as positive flatband voltage shift and hysteresis in capacitance-voltage curves as well as increased interface state density, was observed for SiC-MOS devices with thermally grown oxides. Interestingly, the subsequent annealing of damaged SiO2/SiC samples resulted in superior electrical properties to those for untreated (fresh) devices. These findings imply that UV irradiation of the SiO2/SiC structure is effective for eliciting pre-existing carbon-related defects and transforming them into a simple configuration that can be easily passivated by thermal treatment.

The Electrical Properties and Impedance Analysis of ZnO Varistors Doped with Different Cu2O Contents

2014 ◽  
Vol 681 ◽  
pp. 173-176
Author(s):  
Ji Wei Fan ◽  
Hui Jun Zhao ◽  
Xiao Li Zhang
Keyword(s):  
Electrical Properties ◽  
Grain Boundary ◽  
Leakage Current ◽  
Impedance Analysis ◽  
Boundary Resistance ◽  
Zno Varistors ◽  
Good Agreement

The Cu2O addition deteriorates the electrical properties of ZnO varistors, which is a good agreement with similar findings on Ag2O additions. The best fitted impedance analysis reveals that the Cu2O addition increases grain resistance and lowers the grain boundary resistance, results in low nonlinearity and higher leakage current of ZnO varistors.

Sign in / Sign up

Export Citation Format

Share Document