Multilayer Graphene-Based Carbon Interconnect

2012 ◽  
Vol 1407 ◽  
Author(s):  
Tianhua Yu ◽  
Edwin Kim ◽  
Nikhil Jain ◽  
Bin Yu
Keyword(s):  
Performance Metrics ◽  
Monolayer Graphene ◽  
Multilayer Graphene ◽  
Large Area ◽  
Electrical Stress ◽  
Oxygen Plasma Etching ◽  
Doping Technique ◽  
System Breakdown ◽  
Grown Graphene ◽  
On Chip

ABSTRACT3D stacked (or uncorrelated) multilayer graphene (s-MLG) is investigated as a potential material platform for carbon-based on-chip interconnects. S-MLG samples are prepared by repeatedly transferring and stacking the large-area CVD-grown graphene monolayers, followed by wire patterning and oxygen plasma etching of graphene. We observed superior wire conduction of s-MLG over that of monolayer graphene or ABAB-stacked multilayer graphene. Further reduction of s-MLG resistivity is anticipated with increasing number of stacked layers. Electrical stress-induced doping technique is used to engineer the Dirac point, as well as to reduce graphene-to-metal contact resistance, improving the overall performance metrics of the s-MLG system. Breakdown experiments show that the current-carrying capacity of s-MLG is significantly enhanced as compared with that of monolayer graphene.

Multiple Transfer Used on Repairing Transparent and Electric Film Based on CVD - Grown Graphene

2013 ◽  
Vol 774-776 ◽  
pp. 634-639
Author(s):  
Peng Fei Zhao ◽  
Da Wei He ◽  
Yong Sheng Wang ◽  
Ming Fu ◽  
Hong Peng Wu ◽  
...  
Keyword(s):  
Vapor Deposition ◽  
Gas Flow ◽  
Graphene Film ◽  
Chemical Vapor ◽  
Monolayer Graphene ◽  
Gas Flow Rate ◽  
Large Area ◽  
Spectroscopy Analysis ◽  
Photoelectric Device ◽  
Grown Graphene

We optimized the CH4 and H2 gas flow rate of chemical vapor deposition (CVD) graphene growth and obtained larger area, fewer-layered graphene grown on Cu foils. After transfering to SiO2 substrate by PMMA more than 3 times to repair the defect of monolayer graphene film, we synthesized large area, transparent and continuous graphene film. The morphology and structure were characterized by SEM and Raman spectroscopy. Analysis of electrical properties and optical properties show that we obtained low resistance and high transparency of ~90%, which could be used on photoelectric device as solar cell and acceptable for replacing commercial ITO electrodes.

scholarly journals Unveiling the Direct Correlation between the CVD-Grown Graphene and the Growth Template

2018 ◽  
Vol 2018 ◽  
pp. 1-6 ◽  
Author(s):  
Junghyun Lee ◽  
Jihyung Seo ◽  
Sungchul Jung ◽  
Kibog Park ◽  
Hyesung Park
Keyword(s):  
Graphene Sheet ◽  
Copper Substrate ◽  
Chemical Vapor ◽  
Industrial Applications ◽  
Monolayer Graphene ◽  
Low Carbon ◽  
Large Area ◽  
High Quality ◽  
Carbon Solubility ◽  
Grown Graphene

Chemical vapor deposition (CVD) is known to produce continuous, large-area graphene sheet with decent physical properties. In the CVD process, catalytic metal substrates are typically used as the growth template, and copper has been adopted as the representative material platform due to its low carbon solubility and resulting monolayer graphene growth capability. For the widespread industrial applications of graphene, achieving the high-quality is essential. Several factors affect the qualities of CVD-grown graphene, such as pressure, temperature, carbon precursors, or growth template. In this work, we provide detailed analysis on the direct relation between the metallic growth substrate (copper) and overall properties of the resulting CVD-grown graphene. The surface morphology of copper substrate was modulated via simple chemical treatments, and its effect on physical, optical, and electrical properties of graphene was analyzed. Based on these results, we propose a simple synthesis route to produce high-quality, continuous, monolayer graphene sheet, which can facilitate the commercialization of CVD graphene into reality.

scholarly journals Ultra-Low-Loss Mid-Infrared Plasmonic Waveguides Based on Multilayer Graphene Metamaterials

Nanomaterials ◽  
2021 ◽  
Vol 11 (11) ◽  
pp. 2981
Author(s):  
Chia-Chien Huang ◽  
Ruei-Jan Chang ◽  
Ching-Wen Cheng
Keyword(s):  
Integrated Circuits ◽  
Optical Diffraction ◽  
Multilayer Graphene ◽  
Plasmonic Waveguides ◽  
Large Area ◽  
Mid Infrared ◽  
Optical Signals ◽  
Present Design ◽  
On Chip ◽  
Mode Area

Manipulating optical signals in the mid-infrared (mid-IR) range is a highly desired task for applications in chemical sensing, thermal imaging, and subwavelength optical waveguiding. To guide highly confined mid-IR light in photonic chips, graphene-based plasmonics capable of breaking the optical diffraction limit offer a promising solution. However, the propagation lengths of these materials are, to date, limited to approximately 10 µm at the working frequency f = 20 THz. In this study, we proposed a waveguide structure consisting of multilayer graphene metamaterials (MLGMTs). The MLGMTs support the fundamental volume plasmon polariton mode by coupling plasmon polaritons at individual graphene sheets over a silicon nano-rib structure. Benefiting from the high conductivity of the MLGMTs, the guided mode shows ultralow loss compared with that of conventional graphene-based plasmonic waveguides at comparable mode sizes. The proposed design demonstrated propagation lengths of approximately 20 µm (four times the current limitations) at an extremely tight mode area of 10−6A0, where A0 is the diffraction-limited mode area. The dependence of modal characteristics on geometry and material parameters are investigated in detail to identify optimal device performance. Moreover, fabrication imperfections are also addressed to evaluate the robustness of the proposed structure. Moreover, the crosstalk between two adjacent present waveguides is also investigated to demonstrate the high mode confinement to realize high-density on-chip devices. The present design offers a potential waveguiding approach for building tunable and large-area photonic integrated circuits.

scholarly journals Microarchitectural Characterization on a Mobile Workload

2021 ◽  
Vol 11 (3) ◽  
pp. 1225
Author(s):  
Woohyong Lee ◽  
Jiyoung Lee ◽  
Bo Kyung Park ◽  
R. Young Chul Kim
Keyword(s):  
Performance Monitoring ◽  
Performance Metrics ◽  
Performance Comparison ◽  
Instruction Level Parallelism ◽  
Data Set ◽  
Performance Events ◽  
Hardware Performance Counters ◽  
On Chip ◽  
The Comparative Study ◽  
Level Parallelism

Geekbench is one of the most referenced cross-platform benchmarks in the mobile world. Most of its workloads are synthetic but some of them aim to simulate real-world behavior. In the mobile world, its microarchitectural behavior has been reported rarely since the hardware profiling features are limited to the public. As a popular mobile performance workload, it is hard to find Geekbench’s microarchitecture characteristics in mobile devices. In this paper, a thorough experimental study of Geekbench performance characterization is reported with detailed performance metrics. This study also identifies mobile system on chip (SoC) microarchitecture impacts, such as the cache subsystem, instruction-level parallelism, and branch performance. After the study, we could understand the bottleneck of workloads, especially in the cache sub-system. This means that the change of data set size directly impacts performance score significantly in some systems and will ruin the fairness of the CPU benchmark. In the experiment, Samsung’s Exynos9820-based platform was used as the tested device with Android Native Development Kit (NDK) built binaries. The Exynos9820 is a superscalar processor capable of dual issuing some instructions. To help performance analysis, we enable the capability to collect performance events with performance monitoring unit (PMU) registers. The PMU is a set of hardware performance counters which are built into microprocessors to store the counts of hardware-related activities. Throughout the experiment, functional and microarchitectural performance profiles were fully studied. This paper describes the details of the mobile performance studies above. In our experiment, the ARM DS5 tool was used for collecting runtime PMU profiles including OS-level performance data. After the comparative study is completed, users will understand more about the mobile architecture behavior, and this will help to evaluate which benchmark is preferable for fair performance comparison.

Colorimetric Characterizations of Large Area White OLEDs Under Thermal And Electrical Stress Using TM-30-18 Method

2020 ◽  
Author(s):  
Oussama Ben Abdellah ◽  
Andrea Al Haddad ◽  
Mustapha El Halaoui ◽  
Pascal Dupuis ◽  
Laurent Canale ◽  
...  
Keyword(s):  
Large Area ◽  
Electrical Stress ◽  
White Oleds

Precise Cache Profiling for Studying Radiation Effects

2021 ◽  
Vol 20 (3) ◽  
pp. 1-25
Author(s):  
James Marshall ◽  
Robert Gifford ◽  
Gedare Bloom ◽  
Gabriel Parmer ◽  
Rahul Simha
Keyword(s):  
Radiation Effects ◽  
Fault Injection ◽  
Error Correcting Codes ◽  
Direct Access ◽  
Transient Faults ◽  
Large Area ◽  
Common Multiple ◽  
Single Event Upsets ◽  
On Chip ◽  
Future Work

Increased access to space has led to an increase in the usage of commodity processors in radiation environments. These processors are vulnerable to transient faults such as single event upsets that may cause bit-flips in processor components. Caches in particular are vulnerable due to their relatively large area, yet are often omitted from fault injection testing because many processors do not provide direct access to cache contents and they are often not fully modeled by simulators. The performance benefits of caches make disabling them undesirable, and the presence of error correcting codes is insufficient to correct for increasingly common multiple bit upsets. This work explores building a program’s cache profile by collecting cache usage information at an instruction granularity via commonly available on-chip debugging interfaces. The profile provides a tighter bound than cache utilization for cache vulnerability estimates (50% for several benchmarks). This can be applied to reduce the number of fault injections required to characterize behavior by at least two-thirds for the benchmarks we examine. The profile enables future work in hardware fault injection for caches that avoids the biases of existing techniques.

a-Si TFT Technologies for AM-LCDS

1994 ◽  
Vol 345 ◽  
Author(s):  
Nobuki Ibaraki
Keyword(s):  
Implantation Technique ◽  
Picture Quality ◽  
Large Area ◽  
Aperture Ratio ◽  
Large Size ◽  
Ion Doping ◽  
Doping Technique ◽  
Future Technologies ◽  
Improved Characteristics

AbstractA technical trend for a-Si TFTs is their application to large-size, high-pixel density AMLCDs such as XGA, EWS, and HDTV. In order to realize these LCDs, the TFT device characteristics must be improved. Future technologies, which will be necessary to fabricate TFTs with improved characteristics are as follows,(1) Fully self-aligned TFT technology: A SA-TFT structure reduces the feedthrough voltage caused by parasitic capacitance due to gate/source overlap. This results in an improved picture quality and a higher aperture ratio. Fabrication of such a structure would require ion doping technology.(2) Ion doping technology: This non-mass-separated implantation technique has large area doping capability and much higher doping speed compared to conventional ion implantation technique. The major problems with the ion doping technique is the implantation of unwanted species which deteriorate the quality of source/drain and channel regions of TFTs.

Reducing Design Margins by Adaptive Compensation for Thermal and Aging Variations

2012 ◽  
pp. 201-230
Author(s):  
Zhenyu Qi ◽  
Yan Zhang ◽  
Mircea Stan
Keyword(s):  
Design Parameters ◽  
Worst Case Analysis ◽  
Transimpedance Amplifier ◽  
Large Area ◽  
Negative Bias Temperature Instability ◽  
Worst Case ◽  
Adaptive Computation ◽  
Bias Temperature Instability ◽  
Computation Efficiency ◽  
On Chip

Corner-based design and verification are based on worst-case analysis, thus introducing over-pessimism and large area and power overhead and leading to unnecessary energy consumption. Typical case-based design and verification maximize energy efficiency through design margins reduction and adaptive computation, thus helping achieve sustainable computing. Dynamically adapting to manufacturing, environmental, and usage variations is the key to shaving unnecessary design margins, which requires on-chip modules that can sense and configure design parameters both globally and locally to maximize computation efficiency, and maintain this efficiency over the lifetime of the system. This chapter presents an adaptive threshold compensation scheme using a transimpedance amplifier and adaptive body biasing to overcome the effects of temperature variation, reliability degradation, and process variation. The effectiveness and versatility of the scheme are demonstrated with two example applications, one as a temperature aware design to maintain IONto IOFFcurrent ratio, the other as a reliability sensor for NBTI (Negative Bias Temperature Instability).

scholarly journals Large-Area Thermal Distribution Sensor Based on Multilayer Graphene Ink

Sensors ◽  
2020 ◽  
Vol 20 (18) ◽  
pp. 5188
Author(s):  
Tomi Koskinen ◽  
Taneli Juntunen ◽  
Ilkka Tittonen
Keyword(s):  
Signal To Noise Ratio ◽  
Graphene Film ◽  
Multilayer Graphene ◽  
Wearable Electronics ◽  
Large Area ◽  
Sensor Applications ◽  
Thermal Distribution ◽  
Sensing Applications ◽  
Detection Of Objects ◽  
Distribution Mapping

Emergent applications in wearable electronics require inexpensive sensors suited to scalable manufacturing. This work demonstrates a large-area thermal sensor based on distributed thermocouple architecture and ink-based multilayer graphene film. The proposed device combines the exceptional mechanical properties of multilayer graphene nanocomposite with the reliability and passive sensing performance enabled by thermoelectrics. The Seebeck coefficient of the spray-deposited films revealed an inverse thickness dependence with the largest value of 44.7 μV K−1 at 78 nm, which makes thinner films preferable for sensor applications. Device performance was demonstrated by touch sensing and thermal distribution mapping-based shape detection. Sensor output voltage in the latter application was on the order of 300 μV with a signal-to-noise ratio (SNR) of 35, thus enabling accurate detection of objects of different shapes and sizes. The results imply that films based on multilayer graphene ink are highly suitable to thermoelectric sensing applications, while the ink phase enables facile integration into existing fabrication processes.

Plasmon spectrum of graphene monolayer on substrate

2019 ◽  
Vol 33 (09) ◽  
pp. 1950102
Author(s):  
I. N. Askerzade ◽  
R. T. Askerbeyli
Keyword(s):  
Substrate Material ◽  
Plasmon Mode ◽  
Monolayer Graphene ◽  
Graphene Monolayer ◽  
Multilayer Graphene ◽  
Linear Dispersion ◽  
Long Wavelength ◽  
Theoretical Considerations ◽  
Plasmon Spectrum ◽  
Good Agreement

Plasmon modes in monolayer graphene on substrate are analyzed taking into account the thickness of graphene and substrate material layer in the evaluation of Coulomb potential. It is shown that plasmon mode in graphene monolayer has linear dispersion in contrast to multilayer graphene in long-wavelength limit. The slope of plasmon spectrum is determined by the thickness and dielectric constant of substrate. Obtained results are in good agreement with experimental data and other theoretical considerations.

Sign in / Sign up

Export Citation Format

Share Document