High Power SiC MESFETs

2006 ◽  
Vol 911 ◽  
Author(s):  
Christopher Harris ◽  
Andrei O Konstantinov ◽  
Jan-Olov Svedberg ◽  
Ian Ray ◽  
Christer Hallin
Keyword(s):  
High Power ◽  
High Efficiency ◽  
Total Power ◽  
Short Channel ◽  
Class Ab ◽  
Channel Effects ◽  
Cell Components ◽  
Lateral Epitaxy ◽  
P Type ◽  
Rf Signal

AbstractThe development of high power, high efficiency silicon carbide RF MESFETs is reported. High power densities of over 3W/mm have been measured for devices with total power output in excess of 25W. The devices have been fabricated using a novel lateral epitaxy technique. The MESFET employs a buried p-type depletion stopper in order to suppress short channel effects and increase the operation voltage. The use of the depletion stopper also allows high RF signal gain, while maintaining high voltage operation capability. Single-cell components measured on-wafer demonstrate an Ft of 10 GHz and a high unilateral gain.Packaged 6-mm RF transistors have been evaluated using amplifier circuits designed for operation in classes A, AB or C. Operation in class AB demonstrated a saturated power of 20 W and a P1dB of 15W with a linear gain of over 16 dB at Vdd of 60 V for 2.25 GHz operation. Maximum drain efficiency is 56% for class AB operation, 48% at 1 dB compression point and 72% for class C at 2.25 GHz.

High Power High Efficiency Lateral Epitaxy MESFETs in Silicon Carbide

2006 ◽  
Vol 527-529 ◽  
pp. 1231-1234
Author(s):  
Andrey O. Konstantinov ◽  
J.O. Svedberg ◽  
I.C. Ray ◽  
Chris I. Harris ◽  
Christer Hallin ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Single Cell ◽  
High Power ◽  
High Efficiency ◽  
Large Area ◽  
Short Channel ◽  
Novel Structure ◽  
Channel Effects ◽  
Cell Components ◽  
Lateral Epitaxy

High power high efficiency silicon carbide RF MESFETs are fabricated using a novel structure utilizing lateral epitaxy. The MESFET employs buried p-type depletion stoppers grown by lateral epitaxy with subsequent planarization. The depletion stopper is epitaxially overgrown by the channel layer. The depletion stopper suppresses short channel effects and increases the operation voltage and the RF signal gain at high voltage operation. High breakdown voltages of over 200 Volts are achieved for single-cell components, however large-area transistors are limited to around 150 Volts. Single-cell components measured on-wafer demonstrate an Ft of 10 GHz and high unilateral gain. Packaged 6-mm RF transistors in amplifier circuits feature a saturated power of 20 W and a P1dB of 15W with a linear gain of over 16 dB at Vdd of 60 V for 2.25 GHz operation. Maximum drain efficiency is 56% for class AB operation, 48% at 1 dB compression point and 72% for class C at 2.25 GHz.

Scallop-shaped p-type FinFETs with improved short-channel effects immunity and driving current

2022 ◽  
Vol 140 ◽  
pp. 106337
Author(s):  
Zhaohao Zhang ◽  
Weizhuo Gan ◽  
Junjie Li ◽  
Zhenzhen Kong ◽  
Yanchu Han ◽  
...  
Keyword(s):  
Short Channel Effects ◽  
Short Channel ◽  
Driving Current ◽  
Channel Effects ◽  
P Type

Analysis of Omega-Gate Nanowire SOI MOSFET Under Analog Point of View

2020 ◽  
Vol 15 (1) ◽  
pp. 1-6
Author(s):  
Welder Fernandes Perina ◽  
João Antonio Martino ◽  
Paula Ghedini Der Agopian
Keyword(s):  
Point Of View ◽  
Short Channel Effects ◽  
Theoretical Limit ◽  
Short Channel ◽  
Worst Case ◽  
Channel Effects ◽  
Electrostatic Coupling ◽  
Channel Lengths ◽  
P Type ◽  
New Applications

This paper presents an evaluation of omega-gate nanowire n- and p-type SOI MOSFETs performance focusing on the main analog figures of merit. The different channel widths (WNW) and channel lengths (L) were also evaluated. These devices presented values of subthreshold slope near the theoretical limit at room temperature (60 mV/dec) and in the worst case a DIBL value smaller than 70 mV/V showing its immunity to short channel effects (SCEs) in the range studied. The narrowest device showed great electrostatic coupling, improving transconductance (gm), presenting an unit gain frequency over 200 GHz and intrinsic voltage gain over 80 dB. These values suggests that this device is capable of achieving good performance on new applications such as 5G communications and Internet-of-Things (IoT).

Short-Channel Effects in 4H-SiC MOSFETs

2005 ◽  
Vol 483-485 ◽  
pp. 821-824
Author(s):  
Masato Noborio ◽  
Y. Kanzaki ◽  
Jun Suda ◽  
Tsunenobu Kimoto ◽  
Hiroyuki Matsunami
Keyword(s):  
Threshold Voltage ◽  
Empirical Relationship ◽  
Device Simulation ◽  
Oxide Thickness ◽  
Short Channel Effects ◽  
Short Channel ◽  
Channel Effects ◽  
Channel Lengths ◽  
P Type

Short-channel effects in SiC MOSFETs have been investigated. Planar MOSFETs with various channel lengths have been fabricated on p-type 4H-SiC (0001), (000-1) and (11-20) faces.^Short-channel effects such as punchthrough behavior, decrease of threshold voltage and deterioration of subthreshold characteristics are observed. Furthermore, the critical channel lengths below which short-channel effects occur are analyzed as a function of p-body doping and oxide thickness by using device simulation. The critical channel lengths in the fabricated SiC MOSFETs are in agreement with those obtained from the device simulation. The results are also in agreement with the empirical relationship for Si MOSFETs.

High Power High Efficiency Lateral Epitaxy MESFETs in Silicon Carbide

2006 ◽  
pp. 1231-1234
Author(s):  
Andrey O. Konstantinov ◽  
J.O. Svedberg ◽  
I.C. Ray ◽  
Chris I. Harris ◽  
Christer Hallin ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
High Power ◽  
High Efficiency ◽  
Lateral Epitaxy

Fabrication of L Band 4H-SiC SIT Devices

2013 ◽  
Vol 347-350 ◽  
pp. 1663-1667 ◽  
Author(s):  
Gang Chen ◽  
Hao Jiang ◽  
Shi Chang Zhong ◽  
Song Bai
Keyword(s):  
Current Density ◽  
Total Power ◽  
Power Performance ◽  
Class Ab ◽  
Static Induction Transistors ◽  
L Band ◽  
Lift Off ◽  
P Type ◽  
Recessed Gate ◽  
Gate Recess

Silicon carbide (SiC) static induction transistors (SITs) were fabricated using home-grown epi structures. The gate is a recessed gate - bottom contact (RG - B). The mesa space designed is 2.5 μm and the gate channel is 1.0 μm. The developed devices adopted a p-type Al ion implanted gate and power performance was improved by decreased leakage current and enhanced break-down voltage. The lift-off with assistant dielectric, dense gate recess etching, high temperature anneals and PECVD passivation process technologies are adopted. One cell has 200 source fingers and each source finger width is 50 μm. 0.5 mm SiC SIT yield a current density of 110 mA/mm at a drain voltage of 50 V. A maximum current density of 160 mA/mm was achieved with Vd = 80V, and the maximum transconductance is 40mS/mm. The device blocking voltage with a gate bias of-12 V was 400 V. Packaged 2 × 2-cm devices were evaluated using amplifier circuits designed for class AB operations. A total power output in excess of 70 W was obtained with a power density of 17.5 W/cm and gain of 5.5 dB at L band 1 GHz under pulse 100μs and cycle ratio 1% RF operation and 80V drain to source voltage.

A Novel Power Factor Correction Rectifier for Enhancing Power Quality

2015 ◽  
Vol 6 (4) ◽  
pp. 772 ◽  
Author(s):  
Bindu K V ◽  
B Justus Rabi
Keyword(s):  
Power Factor ◽  
High Power ◽  
High Efficiency ◽  
Power Level ◽  
Harmonic Distortion ◽  
Voltage Regulation ◽  
Total Power ◽  
Front End ◽  
Sinusoidal Input ◽  
Bidirectional Switches

In this paper, the disturbances in power system due to low quality of power are discussed and a current injection method to maintain the sinusoidal input current which will reduce the total current harmonic distortion (THD) as well as improve the power factor nearer to unity is proposed. The proposed method makes use of a novel controlled diode rectifier which involves the use of bidirectional switches across the front-end rectifier and the operation of the converter is fully analyzed. The main feature of the topology is low cost, small size, high efficiency and simplicity, and is excellent for retrofitting front-end rectifier of existing ac drives, UPS etc. A novel strategy implementing reference compensation current depending on the load harmonics and a control algorithm for three-phase three-level unity PF rectifier which draws high quality sinusoidal supply currents and maintains good dc link- voltage regulation under wide load variation. The proposed technique can be applied as a retrofit to a variety of existing thyristor converters which uses three bidirectional switches operating at low frequency and a half-bridge inverter operating at high frequency .The total power delivered to the load is processed by the injection network, the proposed converter offers high efficiency and not only high power factor but also the Total Harmonic Distortion is reduced. Theoretical analysis is verified by digital simulation and a hardware proto type module is implemented in order to confirm the feasibility of the proposed system. This scheme in general is suitable for the common variable medium-to high-power level DC load applications.

scholarly journals Analysis of Circuit Simulation Considering Total Ionizing Dose Effects on FinFET and Nanowire FET

2021 ◽  
Vol 11 (3) ◽  
pp. 894
Author(s):  
Hyeonjae Won ◽  
Myounggon Kang
Keyword(s):  
Circuit Simulation ◽  
Structural Aspect ◽  
Short Channel Effects ◽  
Total Ionizing Dose ◽  
Short Channel ◽  
Dose Effects ◽  
Channel Effects ◽  
Inverter Circuit ◽  
P Type ◽  
Total Ionizing Dose Effects

In this study, we analyzed the total ionizing dose (TID) effect characteristics of p-type FinFET and Nanowire FET (NW-FET) according to the structural aspect through comparison of the two devices. Similar to n-type devices, p-type NW-FETs are less affected than FinFETs by the TID effect. For the inverter TID circuit simulation, both n- and p-types of FinFET and NW-FET were analyzed regarding the TID effect. The inverter operation considering the TID effect was verified using the Berkeley short-channel insulated-gate FET model (BSIM) common multi-gate (CMG) parameters. In addition, an inverter circuit composed of the NW-FET exhibited a smaller change by the TID than that of an inverter circuit composed of the FinFET. Therefore, the gate controllability of the gate-all-around (GAA) device had an excellent tolerance to not only short-channel effects (SCE) but also TID effects.

scholarly journals Hybrid Multimodule DC-DC Converters for Ultrafast Electric Vehicle Chargers

Energies ◽  
2020 ◽  
Vol 13 (18) ◽  
pp. 4949
Author(s):  
Mena ElMenshawy ◽  
Ahmed Massoud
Keyword(s):  
Power Density ◽  
High Power ◽  
High Efficiency ◽  
Controller Design ◽  
Power Level ◽  
Power Converter ◽  
Total Power ◽  
Switching Frequency ◽  
High Power Density ◽  
High Switching Frequency

To increase the adoption of electric vehicles (EVs), significant efforts in terms of reducing the charging time are required. Consequently, ultrafast charging (UFC) stations require extensive investigation, particularly considering their higher power level requirements. Accordingly, this paper introduces a hybrid multimodule DC-DC converter-based dual-active bridge (DAB) topology for EV-UFC to achieve high-efficiency and high-power density. The hybrid concept is achieved through employing two different groups of multimodule converters. The first is designed to be in charge of a high fraction of the total required power, operating at a relatively low switching frequency, while the second is designed for a small fraction of the total power, operating at a relatively high switching frequency. To support the power converter controller design, a generalized small-signal model for the hybrid converter is studied. Also, cross feedback output current sharing (CFOCS) control for the hybrid input-series output-parallel (ISOP) converters is examined to ensure uniform power-sharing and ensure the desired fraction of power handled by each multimodule group. The control scheme for a hybrid eight-module ISOP converter of 200 kW is investigated using a reflex charging scheme. The power loss analysis of the hybrid converter is provided and compared to conventional multimodule DC-DC converters. It has been shown that the presented converter can achieve both high efficiency (99.6%) and high power density (10.3 kW/L), compromising between the two other conventional converters. Simulation results are provided using the MatLab/Simulink software to elucidate the presented concept considering parameter mismatches.

Optimization of SiC MESFET for High Power and High Frequency Applications

2011 ◽  
Vol 679-680 ◽  
pp. 629-632 ◽  
Author(s):  
Niclas Ejebjörk ◽  
Herbert Zirath ◽  
Peder Bergman ◽  
Björn Magnusson ◽  
Niklas Rorsman
Keyword(s):  
Aspect Ratio ◽  
High Power ◽  
High Frequency ◽  
Current Gain ◽  
Short Channel Effects ◽  
Maximum Frequency ◽  
Power Performance ◽  
Short Channel ◽  
Maximum Current ◽  
Channel Effects

SiC MESFETs were scaled both laterally and vertically to optimize high frequency and high power performance. Two types of epi-stacks of SiC MESFETs were fabricated and measured. The first type has a doping of 3×1017 cm-3 in the channel and the second type has higher doping (5×1017 cm-3) in the channel. The higher doping allows the channel to be thinner for the same current density and therefore a reduction of the aspect ratio is possible. This could impede short channel effects. For the material with higher channel doping the maximum transconductance is 58 mS/mm. The maximum current gain frequency, fT, and maximum frequency of oscillation, fmax, is 9.8 GHz and 23.9 GHz, and 12.4 GHz and 28.2 GHz for the MESFET with lower doped channel and higher doping, respectively.

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