3-D Integration Latest Developments at LETI

2006 ◽  
Vol 970 ◽  
Author(s):  
Barbara Charlet
Keyword(s):  
Wafer Bonding ◽  
Crucial Role ◽  
3D Structure ◽  
High Density ◽  
Layer Transfer ◽  
Wafer Level ◽  
Hetero Structure ◽  
Front End ◽  
Integration Approach ◽  
Advanced Packaging

ABSTRACTWe review the latest 3-D integration developments performed in LETI, giving some devices integration examples and discussing the achieved performances. Direct bonding and layer transfer (smart cut™) is now largely used to process innovative substrates like: SOI, SSOI, GeOI, … and others. This type of new substrate can play a crucial role in 3D structure integration and can answer the requirements for new challenging performances.3-D integration approach has been used and will be presented in the following topics: advanced packaging by neo-wafers, chip to wafers integration, hetero-structures integration and wafer to wafer concept (front and back-end application). The examples of neo-wafer rebuilding for advanced packaging, the hetero- structure achieved by chip-to-wafer or wafer-to-wafer bonding and front-end and back-end architecture are discussed regarding the 3-D integration challenging requirements. The challenging cases of wafer-level integrated demonstrators for high density 3D inter-chips connections and wireless interconnections are presented. For some examples we give also the first electrical performances achieved with representative demonstrators.

Development of High Density RDL Technologies for Panel Level Processing

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 000284-000313
Author(s):  
Lars Böttcher ◽  
S. Karaszkiewicz ◽  
F. Schein ◽  
R. Kahle ◽  
A. Ostmann
Keyword(s):  
Coefficient Of Thermal Expansion ◽  
High Density ◽  
Organic Films ◽  
High Yield ◽  
Wafer Level ◽  
Final Size ◽  
Process Yield ◽  
Cu Pillar ◽  
Thin Organic Films ◽  
Advanced Packaging

Advanced packaging technologies like wafer-level fan-out and 3D System-in-Packages (SIPs) are rapidly penetrating the market of electronic components. A recent trend to reduce cost is the extension of processes to large manufacturing formats, called Panel Level Packaging (PLP). In a consortium of German partners from industry and research advanced technologies for PLP are developed. The project aims for an integrated process flow for SIPs with chips embedded into an organic laminate matrix. At first dies with Cu pillar structures are placed into openings of a laminate frame layer with very low coefficient of thermal expansion (CTE). They are embedded by vacuum lamination of thin organic films, filling the very small gap down to 15 μm between chips and frame. The frame provides alignment marks for a local registration of following processes. The ridged frame limits die shift during embedding and gives a remarkable handling robustness. Developments are initially performed on a 305×256mm2 panel format, aiming for a final size of 610×615 mm2. On the top side of embedded chips, a 20μm dielectric film is applied. The goal is to avoid additional via formation and to realize a direct connection between the Cu pillar of the die and the RDL The RDL formation is based on semi-additive processing. Therefore a Ti or TiW barrier and Cu seed layer is sputtered. Subsequently a 7μm photoresist is applied and exposed by a newly developed Direct Imaging (DI) system. Lines and spaces of 4μm were achieved with high yield. In the following, Cu is simultaneously electroplated for the via contacts and interconnects traces. Finally, the photo resist is stripped and the TiW barrier and Cu seed layers are etched. The goal of the development is to provide a technology for a high-density RDL formation on large panel sizes. The paper will discuss the new developments in detail, e.g. the influence of most significant process parameters, like lithographical resolution, minimum via diameter and the placement and alignment accuracy on overall process yield.

Cost-Effective Precision 3D Glass Microfabrication for Advanced Packaging Applications

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 000791-000810
Author(s):  
Jeb Flemming ◽  
Roger Cook ◽  
Kevin Dunn ◽  
James Gouker
Keyword(s):  
Cost Effective ◽  
High Density ◽  
Consumer Electronics ◽  
Liquid Crystal Polymers ◽  
Portable Devices ◽  
Signal Loss ◽  
Wafer Level ◽  
Advanced Packaging ◽  
And Performance ◽  
Optical Waveguiding

Today's packaging has become the limiting element in system cost and performance for IC development. Assembly and packaging technologies have become primary differentiators for manufactures of consumer electronics and the main enabler of small IC product development. Traditional packaging approaches to address the needs in these “High Density Portable” devices, including FR4, liquid crystal polymers, and Low Temperature Co-Fire Ceramics, are running into fundamental limits in packaging layer thinness, high density interconnects (HDI) size and density, and do not present solutions to in-package thermal management, and optical waveguiding. In this talk, 3D Glass Solutions will present on our efforts to create advanced microelectronic packing solutions using our APEX™ Glass ceramic which offers a single material capable of being simultaneously used for ultra-HDI through glass vias (TGVs), optical waveguiding, and in-package microfluidic cooling. In this talk we will discuss our latest results in wafer-level microfabrication of packaging solutions. We will present on our efforts for creating copper filled vias, surface metallization, and passivation. Furthermore, we will present our efforts in exploring this material to produce (1) ultra-HDI glass interposers, with TGVs as small as 12 microns, with 14 micron center –to-center, (2) advanced RF packages with unique surface architectures designed to minimize signal loss, and (3) creating wave guiding structures in HDI packages.

A Robust Thin-Film Wafer-Level Packaging Approach for MEMS Devices

2010 ◽  
Vol 7 (3) ◽  
pp. 175-180 ◽  
Author(s):  
Krishnan Seetharaman ◽  
Bart van Velzen ◽  
Johannes van Wingerden ◽  
Hans van Zadelhoff ◽  
Cadmus Yuan ◽  
...  
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Wafer Bonding ◽  
Sacrificial Layer ◽  
Early Stage ◽  
Bulk Acoustic Wave ◽  
Mems Devices ◽  
Wafer Level ◽  
Front End ◽  
Mems Device

Micro-electromechanical systems (MEMS) devices are extremely sensitive to their environment, especially at the wafer level, until they are packaged in final form. The harsh back-end (BE) operations that the MEMS devices have to endure include dicing, pick-and-place, wire bonding, and molding. During these processing steps, the MEMS device is exposed to particles and contaminants. Therefore, protection at an early stage is a fundamental requirement. We describe a silicon nitride thin-film capping, which is processed using a sacrificial layer technique only with front-end technology. This approach is suitable for mass production of MEMS devices, owing to the fact that it is more cost-effective when compared to other approaches such as wafer-to-wafer bonding and die-to-wafer bonding. A bulk acoustic wave (BAW) resonator that finds application in the radio frequency (RF) front end, for example, in cell phones, is taken as a MEMS vehicle for our work. It is an example of an extremely sensitive MEMS device, because the resonance frequency shifts significantly when additional mass is accidentally deposited on its surface. The thickness of the silicon nitride capping that is required to withstand all the BE steps, in particular transfer molding, is estimated using simple analytical calculations and finite element model (FEM) simulations. The pressure acting on the thin film capping and the thermal load during molding are included in the FEM model. Using this, the minimum thickness required for the capping is determined. We prove that a BAW resonator capped with silicon nitride at the wafer level can be wafer-thinned, diced, wire bonded, and molded without major degradation in performance.

A Robust Wafer-Level Capping Approach for MEMS Devices

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000891-000924
Author(s):  
Krishnan Seetharaman ◽  
Bart van Velzen ◽  
Hans van Zadelhoff ◽  
Cadmus Yuan ◽  
Frank Rietveld ◽  
...  
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Wafer Bonding ◽  
Sacrificial Layer ◽  
Early Stage ◽  
Bulk Acoustic Wave ◽  
Mems Devices ◽  
Wafer Level ◽  
Front End ◽  
Mems Device

Micro-electromechanical systems (MEMS) devices are extremely sensitive to their environment, especially at wafer-level, until they are packaged in final form. The harsh back-end (BE) operations that the MEMS devices have to endure include dicing, pick-and-place, wire bonding and molding. During these processing steps, the MEMS device is exposed to particles and contaminants. Therefore, protection at an early stage is a fundamental requirement. In this work, we describe a silicon nitride thin-film capping, which is processed using a sacrificial layer technique only with front-end technology. This approach is suitable for mass production of MEMS devices, owing to the fact that, it is more cost-effective when compared to other approaches such as wafer-to-wafer bonding and die-to-wafer bonding. A Bulk Acoustic Wave (BAW) resonator, that finds application in the Radio Frequency (RF) front end, e.g., in cell phones, is taken as a MEMS vehicle for our work. It is an example of an extremely sensitive MEMS device, because the resonance frequency shifts significantly when additional mass is accidentally deposited on its surface. The thickness of the silicon nitride capping that is required to withstand all the BE steps, in particular transfer molding, is estimated using simple analytical calculations and finite element model (FEM) simulations. The pressure acting on the thin film capping and the thermal load during molding are included in the FEM model. Using this, the minimum thickness required for the capping is determined. We prove that, a BAW resonator capped with silicon nitride at wafer-level can be wafer-thinned, diced, wire bonded and molded without major degradation in its performance.

High-density-plasma (HDP)-CVD oxide to thermal oxide wafer bonding for strained silicon layer transfer applications

2007 ◽  
Vol 253 (7) ◽  
pp. 3595-3599 ◽  
Author(s):  
R. Singh ◽  
I. Radu ◽  
M. Reiche ◽  
C. Himcinschi ◽  
B. Kuck ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Silicon Layer ◽  
High Density ◽  
Strained Silicon ◽  
Layer Transfer ◽  
Thermal Oxide ◽  
Density Plasma

Characterization of Unfilled Tungsten Plugs on a 0.35μm CMOS Multilevel Metallization Process

1996 ◽  
Author(s):  
H. Sur ◽  
S. Bothra ◽  
Y. Strunk ◽  
J. Hahn
Keyword(s):  
Process Development ◽  
Process Integration ◽  
Wafer Level ◽  
Electrical Failure ◽  
Analysis Techniques ◽  
Integration Approach ◽  
Intermetal Dielectric ◽  
Metallization Process ◽  
Section Analysis

Abstract An investigation into metallization/interconnect failures during the process development phase of an advanced 0.35μm CMOS ASIC process is presented. The corresponding electrical failure signature was electrical shorting on SRAM test arrays and subsequently functional/Iddq failures on product-like test vehicles. Advanced wafer-level failure analysis techniques and equipment were used to isolate and identify the leakage source as shorting of metal lines due to tungsten (W) residue which was originating from unfilled vias. Further cross-section analysis revealed that the failing vias were all exposed to the intermetal dielectric spin-on glass (SOG) material used for filling the narrow spaces between metal lines. The outgassing of the SOG in the exposed regions of the via prior to and during the tungsten plug deposition is believed to be the cause of the unfilled vias. This analysis facilitated further process development in eliminating the failure mechanism and since then no failures of this nature have been observed. The process integration approach used to eliminate the failure is discussed.

U-Net Deep-Learning-Based 3D Cell Counter for the Quality Control of 3D Cell-Based Assays through Seed Cell Measurement

2021 ◽  
pp. 247263032110175
Author(s):  
Eun Ji Jeong ◽  
Donghyuk Choi ◽  
Dong Woo Lee
Keyword(s):  
Quality Control ◽  
Deep Learning ◽  
3D Structure ◽  
High Density ◽  
Cell Counting ◽  
Cell Numbers ◽  
Counting Error ◽  
Seed Cell ◽  
Initial Seed ◽  
Number Of Cells

Conventional cell-counting software uses contour or watershed segmentations and focuses on identifying two-dimensional (2D) cells attached on the bottom of plastic plates. Recently developed software has been useful tools for the quality control of 2D cell-based assays by measuring initial seed cell numbers. These algorithms do not, however, quantitatively test in three-dimensional (3D) cell-based assays using extracellular matrix (ECM), because cells are aggregated and overlapped in the 3D structure of the ECM such as Matrigel, collagen, and alginate. Such overlapped and aggregated cells make it difficult to segment cells and to count the number of cells accurately. It is important, however, to determine the number of cells to standardize experiments and ensure the reproducibility of 3D cell-based assays. In this study, we apply a 3D cell-counting method using U-net deep learning to high-density aggregated cells in ECM to identify initial seed cell numbers. The proposed method showed a 10% counting error in high-density aggregated cells, while the contour and watershed segmentations showed 30% and 40% counting errors, respectively. Thus, the proposed method can reduce the seed cell-counting error in 3D cell-based assays by providing the exact number of cells to researchers, thereby enabling the acquisition of quality control in 3D cell-based assays.

High Precision Low Temperature Direct Wafer Bonding Technology for Wafer-Level 3D ICs Manufacturing

2016 ◽  
Vol 75 (9) ◽  
pp. 345-353 ◽  
Author(s):  
F. Kurz ◽  
T. Plach ◽  
J. Suss ◽  
T. Wagenleitner ◽  
D. Zinner ◽  
...  
Keyword(s):  
Low Temperature ◽  
High Precision ◽  
Wafer Bonding ◽  
Wafer Level ◽  
3D Ics ◽  
Direct Wafer Bonding ◽  
Bonding Technology
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