A Robust Wafer-Level Capping Approach for MEMS Devices

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000891-000924
Author(s):  
Krishnan Seetharaman ◽  
Bart van Velzen ◽  
Hans van Zadelhoff ◽  
Cadmus Yuan ◽  
Frank Rietveld ◽  
...  

Micro-electromechanical systems (MEMS) devices are extremely sensitive to their environment, especially at wafer-level, until they are packaged in final form. The harsh back-end (BE) operations that the MEMS devices have to endure include dicing, pick-and-place, wire bonding and molding. During these processing steps, the MEMS device is exposed to particles and contaminants. Therefore, protection at an early stage is a fundamental requirement. In this work, we describe a silicon nitride thin-film capping, which is processed using a sacrificial layer technique only with front-end technology. This approach is suitable for mass production of MEMS devices, owing to the fact that, it is more cost-effective when compared to other approaches such as wafer-to-wafer bonding and die-to-wafer bonding. A Bulk Acoustic Wave (BAW) resonator, that finds application in the Radio Frequency (RF) front end, e.g., in cell phones, is taken as a MEMS vehicle for our work. It is an example of an extremely sensitive MEMS device, because the resonance frequency shifts significantly when additional mass is accidentally deposited on its surface. The thickness of the silicon nitride capping that is required to withstand all the BE steps, in particular transfer molding, is estimated using simple analytical calculations and finite element model (FEM) simulations. The pressure acting on the thin film capping and the thermal load during molding are included in the FEM model. Using this, the minimum thickness required for the capping is determined. We prove that, a BAW resonator capped with silicon nitride at wafer-level can be wafer-thinned, diced, wire bonded and molded without major degradation in its performance.

2010 ◽  
Vol 7 (3) ◽  
pp. 175-180 ◽  
Author(s):  
Krishnan Seetharaman ◽  
Bart van Velzen ◽  
Johannes van Wingerden ◽  
Hans van Zadelhoff ◽  
Cadmus Yuan ◽  
...  

Micro-electromechanical systems (MEMS) devices are extremely sensitive to their environment, especially at the wafer level, until they are packaged in final form. The harsh back-end (BE) operations that the MEMS devices have to endure include dicing, pick-and-place, wire bonding, and molding. During these processing steps, the MEMS device is exposed to particles and contaminants. Therefore, protection at an early stage is a fundamental requirement. We describe a silicon nitride thin-film capping, which is processed using a sacrificial layer technique only with front-end technology. This approach is suitable for mass production of MEMS devices, owing to the fact that it is more cost-effective when compared to other approaches such as wafer-to-wafer bonding and die-to-wafer bonding. A bulk acoustic wave (BAW) resonator that finds application in the radio frequency (RF) front end, for example, in cell phones, is taken as a MEMS vehicle for our work. It is an example of an extremely sensitive MEMS device, because the resonance frequency shifts significantly when additional mass is accidentally deposited on its surface. The thickness of the silicon nitride capping that is required to withstand all the BE steps, in particular transfer molding, is estimated using simple analytical calculations and finite element model (FEM) simulations. The pressure acting on the thin film capping and the thermal load during molding are included in the FEM model. Using this, the minimum thickness required for the capping is determined. We prove that a BAW resonator capped with silicon nitride at the wafer level can be wafer-thinned, diced, wire bonded, and molded without major degradation in performance.


2012 ◽  
Vol 2012 (DPC) ◽  
pp. 002428-002482
Author(s):  
D. Saint-Patrice ◽  
J. L. Pornin ◽  
B. Savornin ◽  
G. Rodriguez ◽  
S. Danthon ◽  
...  

Most of the time, MEMS devices require hermetic encapsulation for protection against atmosphere, moisture, particles and standard back-end manufacturing technologies. In the last few years, Wafer Level Packaging (WLP) is moving toward developments on Thin Film Packaging (TFP) in order to save footprint, to reduce chip thickness and packaging costs. In the specific case of high-vacuum MEMS encapsulation (gyro, compass), long term pressure stability is required. As the final performances of these kinds of devices are strongly dependent on the working pressure, using TFP for MEMS encapsulation with controlled vacuum becomes more challenging due to very small cavity volumes. It is then necessary to understand the outgassing phenomenon that take place during TFP encapsulation in order to reduce it. In this paper, our latest developments on thin film packaging technology are presented. Outgassing from materials used in TFP and MEMS devices become key parameters to decrease the pressure inside the package and to improve the reliability. In a first part, pressure and Residual Gas Analysis (RGA) of typical TFP and typical MEMS materials are measured under different time / temperature baking processes. Measurements show that material outgassing mainly comes from H2 and maximum pick appears in the beginning of the thermal process. Thanks to these characterizations, an optimized outgassing baking process in term of time and thermal budget is presented. By minimizing the internal outgassing, materials deposited by PVD sputtering can now be implemented as sealing materials for low pressure MEMS devices. In a second part, specific low temperature Al based materials which has been developed on equipment fully compatible with front-end fab is presented. Multi-layer materials like Ti / Al based materials are compared to our single Al based material to decrease the microstructure size and to improve the sealing performances. Scanning Electronic Microscopy (SEM) and Focused Ion Beam (FIB) cross section characterizations confirm that the grain sizes are highly impacted by sputtering process parameters and a compromise has to be done with MEMS outgassing. Finally, the most suitable outgassing baking process for the inside cavity materials and various Al-based sealing materials and stacks are performed for a MEMS compass device on 200 mm wafers. Pressure inside the cavity less than 10 mbar is obtained and the TFP yield is presented on each process conditions. These results are very promising and showed the capabilities of TFP for vacuum MEMS encapsulation applications despite very small volume cavity. Development of such technology is still under way in order to reach high vacuum level in the range of 10-1 to 10-3 mbar.


Nanomaterials ◽  
2021 ◽  
Vol 11 (10) ◽  
pp. 2554
Author(s):  
Wenping Geng ◽  
Xiangyu Yang ◽  
Gang Xue ◽  
Wenhao Xu ◽  
Kaixi Bi ◽  
...  

An integration technology for wafer-level LiNbO3 single-crystal thin film on Si has been achieved. The optimized spin-coating speed of PI (polyimide) adhesive is 3500 rad/min. According to Fourier infrared analysis of the chemical state of the film baked under different conditions, a high-quality PI film that can be used for wafer-level bonding is obtained. A high bonding strength of 11.38 MPa is obtained by a tensile machine. The bonding interface is uniform, completed and non-porous. After the PI adhesive bonding process, the LiNbO3 single-crystal was lapped by chemical mechanical polishing. The thickness of the 100 mm diameter LiNbO3 can be decreased from 500 to 10 μm without generating serious cracks. A defect-free and tight bonding interface was confirmed by scanning electron microscopy. X-ray diffraction results show that the prepared LiNbO3 single-crystal thin film has a highly crystalline quality. Heterogeneous integration of LiNbO3 single-crystal thin film on Si is of great significance to the fabrication of MEMS devices for in-situ measurement of space-sensing signals.


Author(s):  
Wei Chung ◽  
Leonardo Wang ◽  
W. Fang

A new wafer capping process is investigated in this study. The objective of this study is to come out a simple and low cost wafer capping process to make the capped MEMS device wafers “transparent” to traditional IC assembly processes. The carrier wafers with metal mini-caps are bonded on the MEMS device wafers through solder bonding, and the mini-caps are then transferred and left on the MEMS device wafer through a selective etching of the carrier wafers. The metal mini-cap capped device wafers are virtually of the same thickness as original ones; in addition, the transferred metal mini-caps provide a mechanical protection to the MEMS devices during the consequent assembly processes such as wafer dicing, die bonding, molding, etc. With an additional design of 2nd level interconnection on the mini-cap carrier wafer, the transferred MEMS device wafers can be singulated and become a wafer level package with compliant leads.


Author(s):  
Tony Rogers ◽  
Nick Aitken

Wafer bonding is a widely used step in the manufacture of Microsystems, and serves several purposes: • Structural component of the MEMS device. • First level packaging. • Encapsulation of vacuum or controlled gas. In addition the technology is becoming more widely used in IC fabrication for wafer level packaging (WLP) and 3D integration. It is also widely used for the fabrication of micro fluidic structures and in the manufacture of high efficiency LED’s. Depending on the application, temperature constraints, material compatibility etc. different wafer bonding processes are available, each with their own benefits and drawbacks. This paper describes various wafer bonding processes that are applicable, not only to silicon, but other materials such as glass and quartz that are commonly used in MEMS devices. The process of selecting the most appropriate bonding process for the particular application is presented along with examples of anodic, glass frit, eutectic, direct, adhesive and thermo-compression bonding. The examples include appropriate metrology for bond strength and quality. The paper also addresses the benefits of being able to treat the wafer surfaces in-situ prior to bonding in order to improve yield and bond strength, and also discusses equipment requirements for achieving high yield wafer bonding, along with high precision alignment accuracy, good force and temperature uniformity, high wafer throughput, etc. Some common problems that can affect yield are identified and discussed. These include local temperature variations, that can occur with anodic bonding, and how to eliminate them; how to cope with materials of different thermal expansion coefficient; how best to deal with out-gassing and achieve vacuum encapsulation; and procedures for multi-stacking wafers of differing thicknesses. The presentation includes infra-red and scanning acoustic microscopy images of various bond types, plus some examples of what can go wrong if the correct manufacturing protocol is not maintained.


1999 ◽  
Vol 557 ◽  
Author(s):  
M. Boucinha ◽  
V. Chu ◽  
V. Soares ◽  
J. P. Condee

AbstractSurface micromachining is used with amorphous silicon, microcrystalline silicon, silicon nitride and aluminum films as structural materials to form bridge and cantilever structures. Low temperature processing (between 110 and 250 °C) allowed fabrication of structures and devices on glass substrates. Two processes involving different materials as the sacrificial layer are presented: silicon nitride and photoresist. The mechanical integrity of the fabricated structures is discussed. As examples of possible device applications of this technology, air-gap thin film transistors and the electrostatic actuation of bridges and cantilevers are presented.


2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000937-000986
Author(s):  
Souchon Frederic ◽  
Gervais Anne-Charlotte ◽  
Thouy Laurent ◽  
Saint-Patrice Damien ◽  
Pornin Jean louis

MEMS Wafer Level Packaging is required for mass production of MEMS devices: wafer to wafer bonding is usually the current solution, however thin film encapsulation becomes a promising alternative method [1]. Nevertheless, major challenges should be overcome to develop thin film encapsulation, namely the development of a thin cap strong enough to withstand high mold pressures. Consequently, design tools are required to develop successfully thin film encapsulation [2–4]. For that, finite element models (FEM) are commonly used, and this article proposes a generic methodology based on an efficient convergence loop to fit FEM results with experimental data. Our convergence loop guarantees reliable predictive FEM results because our results are double checked with experimental characterizations: we use not only the cap geometry evolution during the process flow, but also the mechanical properties of the cap and especially its stiffness. A study case which shows how to manage the cap deflection during the cap release operation is used to illustrate the relevance of our methodology. To recall [5], the thin film encapsulation requires closed cavities formed above the MEMS devices with surface micromachining techniques: the cavity is formed with a sacrificial layer recovered by a cap. The cap is then perforated by holes to remove the sacrificial layer. Finally, a film is deposited on the cap to seal the cap holes. In practice, the release of the sacrificial layer is one of the most critical operations because the cap can damage the MEMS device due to a buckling effect. Indeed, the residual stresses within the capping layer (compressive residual stresses are usually mandatory) and the geometry of the sacrificial layer have to be tuned in order to control the final shape of the cap. The study case is focused on a test structure with a silicon oxide quadratic plate of 800 μm side length and 3 μm thickness. In practice, the cap geometry has been characterized with a mechanical profilometer; and, a force/displacement curve obtained by nano-indentation technique has been used to extract accurately the mechanical properties of the cap. Then, these experimental data have been used to build our FEM model. The correlation between experimental data and FEM results allows verifying our model because we show that the simulated profile and the simulated stiffness fit successfully with experimental data. The best result has been obtained with a 60MPa compressive residual stress; and, this value is in agreement with experimental measurements. We have used our FEM model to detail the effect of several parameters like the silicon oxide thickness, the residual stresses, the height of the cap edge rolls, or the added value of reinforcement solutions as corrugated membrane or metallic layer. Finally, we conclude that our model is an efficient design tool to optimize the thin film encapsulation. For example, it becomes possible to monitor the buckling effect of the cap by the cavity geometry or the cap material residual stresses.


Author(s):  
John Heck ◽  
Hanan Bar ◽  
Tsung-Kuan A. Chou ◽  
Quan Tran ◽  
Qing Ma ◽  
...  

This paper describes a unique method of encapsulating MEMS switches at the wafer level using a thin-film “microshell” lid and a novel micro-embossing, or “stamping” technique to seal the lid. After fabrication of the MEMS switch and subsequent formation of the microshell, the switches are released through gold tunnels that allow the penetration of a chemical etchant. In a controlled ambient, a “stamp” wafer is aligned to the device wafer, and the wafers are thermally compressed together. This process applies pressure across each tunnel to fuse the gold, thereby sealing the microshell packages. By sealing and passivating the switches at the wafer level, the wafers can be exposed to backend processing, packaging, and assembly steps such as dicing without damaging the sensitive MEMS devices. Furthermore, the size, cost, and complexity of the packaged system are significantly reduced compared to standard wafer bonding processes.


2002 ◽  
Vol 748 ◽  
Author(s):  
Jennifer L. Ruglovsky ◽  
Young-Bae Park ◽  
Cecily A. Ryan ◽  
Harry A. Atwater

ABSTRACTWe report on the layer transfer of thin ferroelectric materials onto silicon substrates. H+ and He+ ion implantation created a buried sacrificial layer in the c-cut BaTiO3 and LiNbO3 single crystals. Bubble formation and thermodynamics of cavity at the bonding interface have been investigated, and single crystal thin film layers were transferred onto crystalline silicon substrates. We have found that defects generated by ion implantation in ferroelectric materials can be significantly recovered with the subsequent annealing for layer splitting.


Author(s):  
James Lee ◽  
Tony Rogers

A novel wafer level packaging method suitable for low production volumes, R&D, and multi-project wafers is presented, providing a hermetic seal suitable for vacuum encapsulation with wafers bonded at a low temperature. Hermetic through-wafer interconnects are bump bonded to a CMOS chip encapsulated by bonding a cap wafer after activating surfaces with free radicals, the Silicon-Silicon direct bond is then annealed to a high strength at 200°C to avoid chip damage. The application for which this system is proposed is an implantable multi-contact active nerve electrode for the treatment of epilepsy via vagus nerve stimulation. Although intended for human implantation of integrated systems, this technology may be applied across a range of devices requiring hermetic or vacuum sealing and through-wafer interconnection. Solid electroplated through-wafer interconnects (aspect ratio 5) enable hermetic interconnection of direct bonded packages with low connection impedance, offering benefits across a range of packaging applications. A key feature of this packaging method is it’s versatility, the proposed embodiment features chip to wafer bonding with an ASIC, but the package is equally suitable for MEMS devices and also for wafer to wafer bonding.


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