A Lithography-Based Compliant Chip-to-Substrate Wafer-Level Interconnect

2002 ◽  
Author(s):  
Qi Zhu ◽  
Lunyu Ma ◽  
Suresh K. Sitaraman
Keyword(s):  
High Performance ◽  
Coefficient Of Thermal Expansion ◽  
Low Cost ◽  
Optimization Technique ◽  
Cost Effective ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Wafer Level ◽  
Good Reliability ◽  
Mechanical Compliance

As the rapid advances in IC design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great advantages for next-generation packaging. β-fly is designed as a compliant chip-to-substrate interconnect for performing wafer-level probing and for packaging without underfill. β-fly has good compliance in all directions to compensate the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of β-fly is similar to standard IC fabrication, and wafer-level packaging makes it cost effective. In this work, self-weight effect and stress distribution under planar displacement loading of β-fly is studied. The effect of geometry parameters on mechanical and electrical performance of β-fly is also studied. β-fly with thinner and narrower arcuate beams with larger radius and taller post is found to have better mechanical compliance. In addition to mechanical compliance, electrical characteristics of β-fly have also been studied in this work. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of β-fly. Response surface methodology and an optimization technique have been used to select the optimal β-fly structure parameters.

Development of G-Helix Structure as Off-Chip Interconnect

2004 ◽  
Vol 126 (2) ◽  
pp. 237-246 ◽  
Author(s):  
Qi Zhu ◽  
Lunyu Ma ◽  
Suresh K. Sitaraman
Keyword(s):  
Mechanical Performance ◽  
Coefficient Of Thermal Expansion ◽  
Mechanical Analysis ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Package Weight ◽  
Mechanical Compliance ◽  
Cte Mismatch

Microsystem packages continue to demand lower cost, higher reliability, better performance and smaller size. Compliant wafer-level interconnects show great potential for next-generation packaging. G-Helix, an electroplated compliant wafer-level chip-to-substrate interconnect can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The fabrication of the G-Helix interconnect is similar to conventional IC fabrication process and is based on electroplating and photolithography. G-Helix interconnect has good mechanical compliance in the three orthogonal directions and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate. In this paper, we report the wafer-level fabrication of an area-arrayed G-Helix interconnects. The geometry effect on the mechanical compliance and electrical parasitics of G-Helix interconnects have been studied. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is also found that structures with excellent mechanical compliance may not have good electrical performance. Therefore, a trade off is needed. Using response surface methodology (RSM), an optimization has been done. Furthermore, reliability of the optimized G-helix interconnects in a silicon-on-organic substrate assembly has been assessed, which includes the package weight and thermo-mechanical analysis. The pitch size effect on the electrical and mechanical performance of G-Helix interconnects has also been studied.

Study of Electroplated Compliant G-Helix Chip-to-Substrate Interconnects

2003 ◽  
Author(s):  
Qi Zhu ◽  
Lunyu Ma ◽  
Suresh K. Sitaraman
Keyword(s):  
Lower Cost ◽  
Coefficient Of Thermal Expansion ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Cross Section Area ◽  
Section Area ◽  
Mechanical Compliance ◽  
Cte Mismatch

Microsystem packages continue to demand lower cost, higher reliability, better performance and smaller size. Compliant wafer-level interconnects show great potential for next-generation packaging. G-Helix, an electroplated compliant wafer-level chip-to-substrate interconnect can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The fabrication of the G-Helix interconnect is similar to conventional IC fabrication process and is based on electroplating and photolithography. G-Helix interconnect has good mechanical compliance in the three orthogonal directions and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate. In this paper, we report the wafer-level fabrication of an area-arrayed G-Helix interconnects. The geometry effect on the mechanical compliance and electrical parasitics of G-Helix interconnects have been studied. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is also found that structures with excellent mechanical compliance may not have good electrical performance. Therefore, a trade off is needed. Using response surface methodology (RSM), an optimization has been done, and the optimal compliant G-Helix interconnect will have a total standoff height of 64 μm, radius of 36 μm and cross-section area of 93 μm2.

A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance

2007 ◽  
Vol 129 (4) ◽  
pp. 460-468 ◽  
Author(s):  
Karan Kacker ◽  
Thomas Sokol ◽  
Wansuk Yun ◽  
Madhavan Swaminathan ◽  
Suresh K. Sitaraman
Keyword(s):  
Flip Chip ◽  
Dielectric Material ◽  
Coefficient Of Thermal Expansion ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Integrative Approach ◽  
Wafer Level ◽  
Target Values ◽  
Low K

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 80 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnects are less likely to crack or delaminate the low-k dielectric material in current and future integrated circuits. The interconnects are potentially cost effective because they can be fabricated in batch at the wafer level and using conventional wafer fabrication infrastructure. In this paper, we present an integrative approach, which uses interconnects with varying compliance and thus varying electrical performance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermomechanical reliability concerns. The test vehicle design to assess the reliability and electrical performance of the interconnects is also presented. Preliminary fabrication results for the integrative approach are presented and show the viability of the fabrication procedure. The results from reliability experiments of helix interconnects assembled on an organic substrate are also presented. Initial results from the thermal cycling experiments are promising. Results from mechanical characterization experiments are also presented and show that the out-of-plane compliance exceeds target values recommended by industry experts. Finally, through finite element analysis simulations, it is demonstrated that the die stresses induced by the compliant interconnects are an order of magnitude lower than the die stresses in flip chip on board (FCOB) assemblies, and hence the compliant interconnects are not likely to crack or delaminate low-k dielectric material.

Advanced 3D eWLB-SiP (embedded Wafer Level Ball Grid Array – System in Package) Technology

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-20
Author(s):  
Seung Wook Yoon
Keyword(s):  
Form Factor ◽  
Power Efficiency ◽  
High Performance ◽  
Electrical Characterization ◽  
Cost Effective ◽  
Electrical Performance ◽  
Wearable Electronics ◽  
Wafer Level ◽  
Low Profile ◽  
Line Spacing

FO-WLP (Fan-Out Wafer Level Packaging) has been established as one of the most versatile packaging technologies in the recent past and is already accounting for a market value of over 1 billion USD due to its unique advantages. The technology combines high performance, increased functionality with a high potential for heterogeneous integration and reduce the total form factor as well as cost-effectiveness. The emerging of advanced of silicon node technology down to 10 nanometer (nm) in support of higher performance, bandwidth and better power efficiency in mobile products pushes the boundaries of emerging packaging technologies to smaller form-factor packaging designs with finer line/spacing as well as improved thermal electrical/performance and integration of SiP or 3D capabilities. Advanced eWLB FO-WLP technology provides a versatile platform for the semiconductor industry's technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D System-in-Package (SiP) configurations. This paper reports developments that extend multi-die and 3D SiP applications with eWLB technology, including ultra thin devices or/and with an interposer substrate attachment. Test vehicles have been designed and fabricated to demonstrate and characterize integrated packaging solutions for network, mobile products including IoT and wearable electronics. The test vehicles have ranged from ~30mm2 to large sizes up to ~230mm2 and 0.4mm ball pitch. Assembly process details including 3D vertical interconnect, laser ablation, RDL processes and mechanical reliability characterizations are to be discussed with component and board level reliability results. In addition, warpage behavior and the PoP stacking process will also be presented. Innovative structure optimization that provides dual advantages of both height reduction and enhanced package reliability are reported. To enable higher interconnection density and signal routing, packages with multiple redistribution layers (RDL) and fine line/width spacing are fabricated and implemented on the eWLB platform. Successful reliability and electrical characterization results on multi-die and 3D eWLB-SiP configurations are reported as an enabling technology for highly integrated, miniaturized, low profile and cost effective solutions.

scholarly journals Design and Demonstration of Glass Panel Embedding for 3D System Packages for Heterogeneous Integration Applications

2019 ◽  
Vol 16 (3) ◽  
pp. 124-135 ◽  
Author(s):  
Siddharth Ravichandran ◽  
Shuhei Yamada ◽  
Tomonori Ogawa ◽  
Tailong Shi ◽  
Fuhan Liu ◽  
...  
Keyword(s):  
Form Factor ◽  
High Performance ◽  
Coefficient Of Thermal Expansion ◽  
Large Body ◽  
Electrical Performance ◽  
Heterogeneous Integration ◽  
Wafer Level ◽  
Glass Panel ◽  
Packaging Technology ◽  
3D Packaging

Abstract This article demonstrates a next-generation high-performance 3D packaging technology with smaller form factor, excellent electrical performance, and reliability for heterogeneous integration. High-density logic-memory integration, today, is built predominantly using interposers which are fundamentally limited in assembly pitch and interconnect lengths, and they also are expensive as the package sizes increase. On the other hand, high-frequency applications continue to use laminates which are also limited by package size and ability to integrate many components. Wafer-level fan-out (WLFO) packaging promises better performance and form factor at lower costs, but current WLFO packages are mold-based and hence are limited to small packages. This article presents a 3D packaging technology using glass panel embedding (GPE) for high-performance with potential for large body size heterogeneous integration applications. The tailorable coefficient of thermal expansion of glass allows a reliable direct board attach of large GPE packages that not only benefits the form factor and signal speed but also provides radical benefits to power delivery. Unlike interposers and silicon bridges, GPE packages are not bump-limited and can support I/O densities comparable with backend-of-line with silicon-like redistribution wiring at much lower costs. The fundamental limitations such as die shift and poor dimensional stability of current organic WLFO packages are addressed by parametric process improvements to reduce die shift to <2 μm while also improving the RDL surface planarity for high-yielding fine-line structures and integrating through glass via (TGV) in the fan-out region for 3D packaging. This article describes the fabrication process for 3D GPE, leading to demonstration of a technology using embedding of chips with all-Cu interconnections at 40-μm I/O pitch with TGVs at 300-μm pitch, thus enabling double-side RDL and assembly of chips to achieve three levels of device integration.

Azo (Hydrazone) pigments: general principles

2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Robert Christie
Keyword(s):  
High Performance ◽  
Metal Salt ◽  
Low Cost ◽  
Cost Effective ◽  
Precipitation Process ◽  
Ambient Temperatures ◽  
Technical Performance ◽  
Chemical Structures ◽  
General Chemical ◽  
Physical Form

Abstract This paper presents an overview of the general chemical principles underlying the structures, synthesis and technical performance of azo pigments, the dominant chemical class of industrial organic pigments in the yellow, orange, and red shade areas, both numerically and in terms of tonnage manufactured. A description of the most significant historical features in this group of pigments is provided, starting from the discovery of the chemistry on which azo colorants are based by Griess in the mid-nineteenth century, through the commercial introduction of the most important classical azo pigments in the early twentieth century, including products known as the Hansa Yellows, β-naphthol reds, including metal salt pigments, and the diarylide yellows and oranges, to the development in the 1950s and 1960s of two classes of azo pigments that exhibit high performance, disazo condensation pigments and benzimidazolone-based azo pigments. A feature that complicates the description of the chemical structures of azo pigments is that they exist in the solid state as the ketohydrazone rather than the hydroxyazo form, in which they have been traditionally been illustrated. Numerous structural studies conducted over the years on an extensive range of azo pigments have demonstrated this feature. In this text, they are referred to throughout as azo (hydrazone) pigments. Since a common synthetic procedure is used in the manufacture of virtually all azo (hydrazone) pigments, this is discussed in some detail, including practical aspects. The procedure brings together two organic components as the fundamental starting materials, a diazo component and a coupling component. An important reason for the dominance of azo (hydrazone) pigments is that they are highly cost-effective. The syntheses generally involve low cost, commodity organic starting materials and are carried out in water as the reaction solvent, which offers obvious economic and environmental advantages. The versatility of the approach means that an immense number of products may be prepared, so that they have been adapted structurally to meet the requirements of many applications. On an industrial scale, the processes are straightforward, making use of simple, multi-purpose chemical plant. Azo pigments may be produced in virtually quantitative yields and the processes are carried out at or below ambient temperatures, thus presenting low energy requirements. Finally, provided that careful control of the reaction conditions is maintained, azo pigments may be prepared directly by an aqueous precipitation process that can optimise physical form, with control of particle size distribution, crystalline structure, and surface character. The applications of azo pigments are outlined, with more detail reserved for subsequent papers on individual products.

scholarly journals Ultralow-temperature-driven water-based sorption refrigeration enabled by low-cost zeolite-like porous aluminophosphate

2022 ◽  
Vol 13 (1) ◽  
Author(s):  
Zhangli Liu ◽  
Jiaxing Xu ◽  
Min Xu ◽  
Caifeng Huang ◽  
Ruzhu Wang ◽  
...  
Keyword(s):  
Low Temperature ◽  
Water Sorption ◽  
High Performance ◽  
Global Climate ◽  
Low Cost ◽  
Cost Effective ◽  
High Water ◽  
Coefficient Of Performance ◽  
High Efficient ◽  
Water Based

AbstractThermally driven water-based sorption refrigeration is considered a promising strategy to realize near-zero-carbon cooling applications by addressing the urgent global climate challenge caused by conventional chlorofluorocarbon (CFC) refrigerants. However, developing cost-effective and high-performance water-sorption porous materials driven by low-temperature thermal energy is still a significant challenge. Here, we propose a zeolite-like aluminophosphate with SFO topology (EMM-8) for water-sorption-driven refrigeration. The EMM-8 is characterized by 12-membered ring channels with large accessible pore volume and exhibits high water uptake of 0.28 g·g−1 at P/P0 = 0.2, low-temperature regeneration of 65 °C, fast adsorption kinetics, remarkable hydrothermal stability, and scalable fabrication. Importantly, the water-sorption-based chiller with EMM-8 shows the potential of achieving a record coefficient of performance (COP) of 0.85 at an ultralow-driven temperature of 63 °C. The working performance makes EMM-8 a practical alternative to realize high-efficient ultra-low-temperature-driven refrigeration.

Advanced SiP Packaging Technologies of IPD for Mobile Applications

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 1-20
Author(s):  
Geun Sik Kim ◽  
Kai Liu ◽  
Flynn Carson ◽  
Seung Wook Yoon ◽  
Meenakshi Padmanathan
Keyword(s):  
High Performance ◽  
Low Cost ◽  
Autonomous Systems ◽  
System Level ◽  
Design And Technology ◽  
Wafer Level ◽  
Future Technology ◽  
Rf Transceivers ◽  
And Performance ◽  
3D Stacking

IPD technology was originally developed as a way to replace bulky discrete passive components, but it¡¯s now gaining popularity in ESD/EMI protection applications, as well as in RF, high-brightness LED silicon sub-mounts, and digital and mixed-signal devices. Already well known as a key enabler of system-in-packages (SiPs), IPDs enable the assembly of increasingly complete and autonomous systems with the integration of diverse electronic functions such as sensors, RF transceivers, MEMS, power amplifiers, power management units, and digital processors. The application area for IPD will continue to evolve, especially as new packaging technology, such as flipchip, 3D stacking, wafer level packaging become available to provide vertical interconnections within the IPD. New applications like silicon interposers will become increasingly significant to the market. Currently the IPD market is being driven primarily by RF or wireless packages and applications including, but not limited to, cell phones, WiFi, GPS, WiMAX, and WiBro. In particular, applications and products in the emerging RF CMOS market that require a low cost, smaller size, and high performance are driving demand. In order to get right products in size and performance, packaging design and technology should be considered in device integration and implemented together in IPD designs. In addition, a comprehensive understanding of electrical and mechanical properties in component and system level design is important. This paper will highlight some of the recent advancements in SiP technology for IPD and integration as well as what is developed to address future technology requirements in IPD SiP solutions. The advantage and applications of SiP solution for IPD will be presented with several examples of IPD products. The design, assembly and packaging challenges and performance characteristics will be also discussed.

Through Silicon Via Technology: Cost effective Cu-TSV Interconnects by EMC3D and Technical Challenges with Cu-TSV

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000425-000445
Author(s):  
Paul Siblerud ◽  
Rozalia Beica ◽  
Bioh Kim ◽  
Erik Young
Keyword(s):  
Low Cost ◽  
Cost Effective ◽  
High Yield ◽  
Integrated Process ◽  
Wafer Level ◽  
Through Silicon Via ◽  
Wafer Level Packaging ◽  
Current State ◽  
Future Technologies ◽  
Ic Technology

The development of IC technology is driven by the need to increase performance and functionality while reducing size, power and cost. The continuous pressure to meet those requirements has created innovative, small, cost-effective 3-D packaging technologies. 3-D packaging can offer significant advantages in performance, functionality and form factor for future technologies. Breakthrough in wafer level packaging using through silicon via technology has proven to be technologically beneficial. Integration of several key and challenging process steps with a high yield and low cost is key to the general adoption of the technology. This paper will outline the breakthroughs in cost associated with an iTSV or Via-Mid structure in a integrated process flow. Key process technologies enabling 3-D chip:Via formationInsulator, barrier and seed depositionCopper filling (plating),CMPWafer thinningDie to Wafer/chip alignment, bonding and dicing This presentation will investigate these techniques that require interdisciplinary coordination and integration that previously have not been practiced. We will review the current state of 3-D interconnects and the of a cost effective Via-first TSV integrated process.

Application of SU-8 photoresist as a multi-functional structural dielectric layer in FOWLP

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-19
Author(s):  
Raquel Pinto ◽  
André Cardoso ◽  
Sara Ribeiro ◽  
Carlos Brandão ◽  
João Gaspar ◽  
...  
Keyword(s):  
Structural Material ◽  
High Performance ◽  
Microelectromechanical Systems ◽  
Low Cost ◽  
Process Conditions ◽  
Processing Temperature ◽  
Wafer Level ◽  
Fast Growing ◽  
Wide Range ◽  
Different Types

Microelectromechanical Systems (MEMS) are a fast growing technology for sensor and actuator miniaturization finding more and more commercial opportunities by having an important role in the field of Internet of Things (IoT). On the same note, Fan-out Wafer Level Packaging (FOWLP), namely WLFO technology of NANIUM, which is based on Infineon/ Intel eWLB technology, is also finding further applications, not only due to its high performance, low cost, high flexibility, but also due to its versatility to allow the integration of different types of components in the same small form-factor package. Despite its great potential it is still off limits to the more sensitive components as micro-mechanical devices and some type of sensors, which are vulnerable to temperature and pressure. In the interest of increasing FOWLP versatility and enabling the integration of MEMS, new methods of assembling and processing are continuously searched for. Dielectrics currently used for redistribution layer construction need to be cured at temperatures above 200°C, making it one of the major boundary for low temperature processing. In addition, in order to accomplish a wide range of dielectric thicknesses in the same package it is often necessary to stack very different types of dielectrics with impact on bill of materials complexity and cost. In this work, done in cooperation with the International Iberian Nanotechnology Laboratory (INL), we describe the implementation of commercially available SU-8 photoresist as a structural material in FOWLP, allowing lower processing temperature and reduced internal package stress, thus enabling the integration of components such as MEMS/MOEMS, magneto-resistive devices and micro-batteries. While SU-8 photoresist was first designed for the microelectronics industry, it is currently highly used in the fabrication of microfluidics as well as microelectromechanical systems (MEMS) and BIO-MEMS due to its high biocompatibility and wide range of available thicknesses in the same product family. Its good thermal and chemical resistance and also mechanical and rheological properties, make it suitable to be used as a structural material, and moreover it cures at 150°C, which is key for the applications targeted. Unprecedentedly, SU-8 photoresist is tested in this work as a structural dielectric for the redistribution layers on 300mm fan-out wafers. Main concerns during the evaluation of the new WLFO dielectric focused on processability quality; adhesion to multi-material substrate and metals (copper, aluminium, gold, ¦); between layers of very different thicknesses; and overall reliability. During preliminary runs, processability on 300 mm fan-out wafers was evaluated by testing different coating and soft bake conditions, exposure settings, post-exposure parameters, up to developing setup. The outputs are not only on process conditions and results but also on WLFO design rules. For the first time, a set of conditions has been defined that allows processing SU-8 on WLFO, with thickness values ranging from 1 um to 150 um. The introduction of SU-8 in WLFO is a breakthrough in this fast-growing advanced packaging technology platform as it opens vast opportunities for sensor integration in WLP technology.

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