TiN Metallization Barriers: From 1.2μ to 0.35μ Technology

1992 ◽  
Vol 260 ◽  
Author(s):  
Fabio Pintchovski ◽  
Ed Travis
Keyword(s):  
Integrated Circuit ◽  
Electrical Contacts ◽  
Barrier Material ◽  
Aspect Ratios ◽  
Space Saving ◽  
Straight Wall ◽  
Materials Used ◽  
Potential Interactions ◽  
Circuit Technology ◽  
Contact Metal

ABSTRACTThe evolution of modern integrated circuit technology to sub micron dimensions has brought about a number of challenges, specially in the field of metallization. Decreasing junction depths have imposed stringent demands on the materials used for the electrical contacts. This is due to the potential interactions between the contact metal and silicon (or suicide in the case of salicide processes) causing junction leakage and/or shorting. The solution most commonly applied to this problem is that in which a barrier material is interposed between the metallization and the contact. The material most often selected for this purpose has been TiN. TiN can be deposited via the reactive sputtering of Ti in a N2 atmosphere or it can be also obtained by sputtering Ti and then reacting it with either N2 or NH3. Shrinking VLSI dimensions have brought about the need for improved planarization for the purposes of metal definition. It has also prevented the tapering of contacts for space saving reasons. Both of these issues resulted in deep, straight wall contacts with aspect ratios greater than 1 that cannot be metallized appropriately with conventional sputtering techniques. These requirements have driven the development of a conformai CVD TiN barrier process. This paper describes the evolution of the TiN metallization barrier from the requirements of 1.2μ to 0.35μ technologies.

Mechanical Properties of Microsensor Materials: How to Deal with the Process Dependences?

1991 ◽  
Vol 239 ◽  
Author(s):  
Stephen D. Senturia
Keyword(s):  
Thin Film ◽  
Mechanical Properties ◽  
Residual Stress ◽  
Integrated Circuit ◽  
Object Oriented ◽  
Cad System ◽  
Measurement Devices ◽  
Materials Used ◽  
Oriented Material ◽  
Circuit Technology

ABSTRACTMicrosensors are measurement devices fabricated using planar integrated circuit technology together with enhancements generically called “micromachining”. It is well known that the thin-film materials used in microelectronics can have properties which differ from their bulk counterparts. In addition, thin-film materials exhibit residual stress, which is known to be strongly process dependent. The sensor designer must understand how the detailed process used to fabricate a particular device impacts the specific mechanical properties, hence, the expected mechanical device performance. This paper illustrates the problem of process-dependent material properties using examples of residual stress of several materials, and then presents an object-oriented material-property database which is being developed as part of a CAD system for microelectromechan-ical systems (MEMCAD).

Preparation of TEM samples by focused ion beams

1995 ◽  
Vol 53 ◽  
pp. 518-519
Author(s):  
John F. Walker ◽  
J C Reiner ◽  
C Solenthaler
Keyword(s):  
Integrated Circuit ◽  
Polycrystalline Silicon ◽  
Field Effect Transistor ◽  
High Spatial Resolution ◽  
Ion Beam ◽  
Ion Beams ◽  
Focused Ion Beams ◽  
Precise Location ◽  
Effect Transistor ◽  
Circuit Technology

The high spatial resolution available from TEM can be used with great advantage in the field of microelectronics to identify problems associated with the continually shrinking geometries of integrated circuit technology. In many cases the location of the problem can be the most problematic element of sample preparation. Focused ion beams (FIB) have previously been used to prepare TEM specimens, but not including using the ion beam imaging capabilities to locate a buried feature of interest. Here we describe how a defect has been located using the ability of a FIB to both mill a section and to search for a defect whose precise location is unknown. The defect is known from electrical leakage measurements to be a break in the gate oxide of a field effect transistor. The gate is a square of polycrystalline silicon, approximately 1μm×1μm, on a silicon dioxide barrier which is about 17nm thick. The break in the oxide can occur anywhere within that square and is expected to be less than 100nm in diameter.

Emerging Techniques for the Characterization of Nano-Mechanical Properties of Integrated Circuit Components

2008 ◽  
Author(s):  
Nicholas Randall ◽  
Rahul Premachandran Nair
Keyword(s):  
Mechanical Properties ◽  
Quality Control ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Manufacturing Process ◽  
Solder Bumps ◽  
Initial Work ◽  
Circuit Components ◽  
Materials Used

Abstract With the growing complexity of integrated circuits (IC) comes the issue of quality control during the manufacturing process. In order to avoid late realization of design flaws which could be very expensive, the characterization of the mechanical properties of the IC components needs to be carried out in a more efficient and standardized manner. The effects of changes in the manufacturing process and materials used on the functioning and reliability of the final device also need to be addressed. Initial work on accurately determining several key mechanical properties of bonding pads, solder bumps and coatings using a combination of different methods and equipment has been summarized.

PERFORMANCE AT THE EDGE: GALLIUM ARSENIDE AND SILICON ICs FOR OPTICAL ELECTRONICS

1991 ◽  
Vol 02 (03) ◽  
pp. 147-162 ◽  
Author(s):  
ROBERT G. SWARTZ
Keyword(s):  
Gallium Arsenide ◽  
Optical Communication ◽  
Optical Communications ◽  
Integrated Circuit ◽  
High Performance ◽  
Compound Semiconductor ◽  
Performance Curve ◽  
Semiconductor Technology ◽  
Market Trends ◽  
Circuit Technology

Compound semiconductor technology is rapidly entering the mainstream, and is quickly finding its way into consumer applications where high performance is paramount. But silicon integrated circuit technology is evolving up the performance curve, and CMOS in particular is consuming ever more market share. Nowhere is this contest more clearly evident than in optical communications. Here applications demand performance ranging from a few hundreds of megahertz to multi-gigahertz, from circuits containing anywhere from tens to tens of thousands of devices. This paper reviews the high performance electronics found in optical communication applications from a technology standpoint, illustrating merits and market trends for these competing, yet often complementary IC technologies.

Aluminum Reflow Sputtering

MRS Bulletin ◽  
1995 ◽  
Vol 20 (11) ◽  
pp. 53-56 ◽  
Author(s):  
Kuniko Kikuta
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Lower Cost ◽  
High Reliability ◽  
Device Fabrication ◽  
Damascene Process ◽  
Aspect Ratios ◽  
Multi Level ◽  
Poor Adhesion ◽  
Lower Resistivity

The scaling of integrated-circuit device dimensions in the horizontal direction has caused an increase in aspect ratios of contact holes and vias without a corresponding scaledown in vertical dimensions. Conventional sputtering has become unreliable for handling higher aspect-ratio via/contact holes because of its poor step coverage. Several studies have attempted to overcome this problem by using W-CVD and reflow technology. The W-CVD is used for practical device fabrications. However, this technique has several problems such as poor adhesion to SiO2, poor W surface morphology, greater resistivity than Al, and the need of an etch-back process.Al reflow technology using a conventional DC magnetron sputtering system can simplify device-fabrication processes and achieve high reliability without Al/W interfaces. In particular, the Al reflow technology is profitable for multi-level interconnections in combination with a damascene process by using Al chemical mechanical polishing (CMP). These interconnections are necessary for miniaturized and high-speed devices because they provide lower resistivity than W and simplify fabrication processes, resulting in lower cost.This article describes recent Al reflow sputtering technologies as well as application of via and interconnect metallization.

scholarly journals Design and Development of a 3dB Quadrature Patch Hybrid Coupler

2018 ◽  
Vol 7 (2.6) ◽  
pp. 217
Author(s):  
B Sekharbabu ◽  
K Narsimha Reddy ◽  
S Sreenu
Keyword(s):  
Integrated Circuit ◽  
High Frequency ◽  
Return Loss ◽  
Coupling Factor ◽  
Power Combiners ◽  
Measurement Results ◽  
Structure Simulation ◽  
Hybrid Coupler ◽  
Port Device ◽  
Circuit Technology

In this paper a -3 dB, 90-degreephase shift RF quadrature patch hybrid coupler is designed to operate at 2.4GHz. Hybrid coupler is a four-port device, that’s accustomed split a signaling with a resultant 90degrees’ section shift between output signals whereas maintaining high isolation between the output ports. The RF quadrature patch hybrid coupler is used in various radio frequency applications including mixers, power combiners, dividers, modulators and amplifiers. The desired hybrid coupler is designed using FR-4 substrate with 1.6mm height in High Frequency Structure Simulation (HFSS) and the same is fabricated and tested. The designed Hybrid coupler is examined in terms of parameters like insertion Loss, coupling factor and return Loss. The simulation and measurement results are compared. Major advantages of the RF quadrature patch hybrid couplers are that they are compatible with integrated circuit technology.

Conversion Method of Description Files in Structural Testing of Digital Circuit

2013 ◽  
Vol 427-429 ◽  
pp. 1285-1288
Author(s):  
Kang Yi Wang
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Digital Circuit ◽  
Logic Circuit ◽  
Structural Testing ◽  
Digital Logic ◽  
Continuous Development ◽  
Program Correctness ◽  
Testing Program ◽  
Circuit Technology

With the continuous development of large-scale integrated circuit technology, the importance of structural testing and testability design for digital logic circuit has become increasingly evident. In the testing domain, Bench is the most commonly used formats to describe a measured circuit. In order to test the measured circuit using computer, files with various formats must be converted to a netlist file which can be identified by computer. Lev format is a common netlist file. This paper mainly discusses how to convert the Bench file into Lev file, and it is proved by testing program correctness and robustness.

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