High Channel Mobility a-Si:H Thin Film Transistors with Oxide/Nitride Dielectrics

1992 ◽  
Vol 284 ◽  
Author(s):  
S. S. He ◽  
D. J. Stephens ◽  
G. Lucovsky ◽  
R. W. Hamaker
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Gas Flow ◽  
Nitride Layer ◽  
Device Fabrication ◽  
Interfacial Region ◽  
Channel Mobility ◽  
Gate Structure ◽  
Gas Flow Ratio ◽  
Nitride Layers

ABSTRACTWe describe: i) nitride-layer optimization; ii) device fabrication: and iii) electrical properties of a-Si:H thin film transistors, TFTs, that integrate oxide/nitride dielectrics into an inverted, staggered gate structure. We have systematically changed the concentrations of Si-Si, Si-H and Si-NH bonding groups within the deposited nitride layers by varying the source gas flow ratio, R = NH3/SiH4 from 2.5 to 12.5. The electrical characteristics of the TFTs improve significantly as the gas phase ratio R is increased from 2.5 to approximately 10, and then decrease as R is further increased. The performance of the TFTs peaks for a source gas ratio of -10, where the channel mobility is ∼1.4 cm2/V-s, the threshold voltage is 2.3 V; and the Ion to Ioff current ratio is > 105.These increases in performance can only realized in devices in which the back of the Si channel region is passivated with an oxy-nitride interfacial region.

High Mobility ZnO thin film transistors using the novel deposition of high-k dielectrics

2011 ◽  
Vol 1315 ◽  
Author(s):  
D. K. Ngwashi ◽  
R. B. M. Cross ◽  
S. Paul ◽  
Andrian P. Milanov ◽  
Anjana Devi
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Performance Metrics ◽  
Chemical Vapour ◽  
High Mobility ◽  
Hafnium Dioxide ◽  
Organic Chemical ◽  
Channel Mobility ◽  
High K ◽  
Metal Organic

ABSTRACTIn order to investigate the performance of ZnO-based thin film transistors (ZnO-TFTs), we fabricate devices using amorphous hafnium dioxide (HfO2) high-k dielectrics. Sputtered ZnO was used as the active channel layer, and aluminium source/drain electrodes were deposited by thermal evaporation, and the HfO2 high-k dielectrics are deposited by metal-organic chemical vapour deposition (MOCVD). The ZnO-TFTs with high-k HfO2 gate insulators exhibit good performance metrics and effective channel mobility which is appreciably higher in comparison to SiO2-based ZnO TFTs fabricated under similar conditions. The average channel mobility, turn-on voltage, on-off current ratio and subthreshold swing of the high-k TFTs are 31.2 cm2V-1s-1, -4.7 V, ~103, and 2.4 V/dec respectively. We compared the characteristics of a typical device consisting of HfO2 to those of a device consisting of thermally grown SiO2 to examine their potential for use as high-k dielectrics in future TFT devices.

Analytical Treatment of Field-Effect Conduction in Polysilicon thin film Transistors

1997 ◽  
Vol 471 ◽  
Author(s):  
W. Eccleston
Keyword(s):  
Thin Film ◽  
Grain Size ◽  
Thin Film Transistors ◽  
Field Effect ◽  
Drain Current ◽  
High Current ◽  
Analytical Treatment ◽  
Channel Mobility ◽  
Current Region ◽  
The Relationship

ABSTRACTThe drift of electrons in the channels of Thin Film Transistors is analysed for discrete grains separated by grain boundaries containing amorphous silicon. The model provides the relationship channel mobility and grain size. The relationship between drain current and the terminal voltages is also predicted. The model relates to normal high current region of transistor operation.

Pentacene Thin-Film Transistors and Inverters with Dual-Gate Structure

2006 ◽  
Vol 9 (11) ◽  
pp. G320 ◽  
Author(s):  
Jae Bon Koo ◽  
Jung Wook Lim ◽  
Seong Hyun Kim ◽  
Chan Hoe Ku ◽  
Sang Chul Lim ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Gate Structure ◽  
Dual Gate

Development of Top-Gate Nanocrystalline Si:H Thin Film Transistors

2004 ◽  
Vol 808 ◽  
Author(s):  
Jarrod McDonald ◽  
Vikram L. Dalal ◽  
Max Noack
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Breakdown Strength ◽  
Defect Density ◽  
Hydrogen Plasma ◽  
Interface State ◽  
Nitride Layer ◽  
High Ratio ◽  
X Ray Diffraction ◽  
X Ray

ABSTRACTWe report on the growth and fabrication of top gate thin film transistors at low temperatures in nanocrystalline Si:H. The nanocrystalline Si:H was deposited using a VHF-PECVD plasma process at 45 MHz in a diode reactor. The material was deposited from a mixture of silane and hydrogen at a temperature of 250-300°C. Higher temperatures resulted in a loss of hydrogen from the material. The properties of the nanocrystalline Si:H were studied using x-ray diffraction and Raman spectroscopy. The material showed a high ratio (3.8) between the crystalline and amorphous peaks in the Raman spectrum. X-ray diffraction data showed the films to be predominantly oriented in <111> direction, and the grain size estimated from Scherer's formula was in the range of 12-15 nm. The doping of the material could be changed by introducing ppm levels of Boron or Phosphorus. The as-grown material was generally n type. By adding controlled amounts of B, the material could be made p type. The devices made were n-channel MISFET's with p body. The n+ source and drain layers were made from amorphous Si:H. A systematic investigation of the appropriate oxide/nitride layer to be used was undertaken. The nitride layers were grown at 250-300°C using mixtures of silane and ammonia, with a high degree of dilution by helium. The presence of helium dilution, along with post-deposition passivation by a hydrogen plasma, was found to produce reproducible, low interface defect density nitride materials. Interface state densities were measured using capacitance spectroscopy at different frequencies and temperatures and found to be in the range of 4.5x1011/cm2-eV. The breakdown strength of the nitride was measured and found to be 4 MV/cm. Proof-of-concept TFT devices were fabricated using reactive ion etching. The threshold voltage was in the range of 13-15 V, and the on/off ratio was in the range of 103.

Comparative study of mobility extraction methods in p-type polycrystalline silicon thin film transistors

2017 ◽  
Vol 31 (19-21) ◽  
pp. 1740007
Author(s):  
Kai Liu ◽  
Yuan Liu ◽  
Yu-Rong Liu ◽  
Yun-Fei En ◽  
Bin Li
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Localized States ◽  
Silicon Thin Film ◽  
Linear Region ◽  
Channel Mobility ◽  
Source Voltage ◽  
P Type ◽  
Voltage Region

Channel mobility in the p-type polycrystalline silicon thin film transistors (poly-Si TFTs) is extracted using Hoffman method, linear region transconductance method and multi-frequency C-V method. Due to the non-negligible errors when neglecting the dependence of gate-source voltage on the effective mobility, the extracted mobility results are overestimated using linear region transconductance method and Hoffman method, especially in the lower gate-source voltage region. By considering of the distribution of localized states in the band-gap, the frequency independent capacitance due to localized charges in the sub-gap states and due to channel free electron charges in the conduction band were extracted using multi-frequency C-V method. Therefore, channel mobility was extracted accurately based on the charge transport theory. In addition, the effect of electrical field dependent mobility degradation was also considered in the higher gate-source voltage region. In the end, the extracted mobility results in the poly-Si TFTs using these three methods are compared and analyzed.

Pentacene Organic Thin-Film Transistors with Dual-Gate Structure

2007 ◽  
Vol 124-126 ◽  
pp. 383-386
Author(s):  
Jae Bon Koo ◽  
Jung Wook Lim ◽  
Chan Hoe Ku ◽  
Sang Chul Lim ◽  
Jung Hun Lee ◽  
...  
Keyword(s):  
Thin Film ◽  
Electrostatic Potential ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Atomic Layer ◽  
Organic Thin Film Transistors ◽  
Organic Thin Film ◽  
Gate Structure ◽  
Dual Gate ◽  
Bottom Gate

We report on the fabrication of dual-gate pentacene organic thin-film transistors (OTFTs) using a plasma-enhanced atomic layer deposited (PEALD) 150 nm thick Al2O3 as a bottom gate dielectric and a 300 nm thick parylene or a PEALD 200 nm thick Al2O3 as both a top gate dielectric and a passivation layer. The threshold voltage (Vth) of OTFT with a 300 nm thick parylene as a top gate dielectric is changed from 4.7 V to 1.3 V and that with a PEALD 200 nm thick Al2O3 as a top gate dielectric is changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode is changed from -10 V to 10 V. The change of Vth of OTFT with the dual-gate structure has been successfully understood by an analysis of electrostatic potential.

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