Rapid Thermal Oxidation of Lightly Doped Silicon in N2O

1994 ◽  
Vol 342 ◽  
Author(s):  
S.C. Sun ◽  
L.S. Wang ◽  
F.L. Yeh ◽  
T.S. Lai ◽  
Y.H. Lin
Keyword(s):  
Growth Rate ◽  
Thermal Oxidation ◽  
Charge Trapping ◽  
Interface State ◽  
Constant Current ◽  
Mos Capacitor ◽  
Rapid Thermal Oxidation ◽  
Doped Silicon ◽  
State Generation ◽  
First Time

ABSTRACTIn this paper, a detailed study is presented for the growth kinetics of rapid thermal oxidation of lightly-doped silicon in N2O and O2 on (100), (110), and (111) oriented substrates. It was found that (110)-oriented Si has the highest growth rate in both N2O and dry O2, and (100) Si has the lowest rate. There is no “crossover” on the growth rate of rapid thermal N2O oxidation between (110) Si and (111) Si as compared to oxides grown in furnace N2O. Pressure dependence of rapid thermal N2O oxidation is reported for the first time. MOS capacitor results show that the low-pressure (40 Torr) N2O-grown oxides have much less interface state generation and charge trapping under constant current stress as compared to oxides grown in either 760 Torr N2O or O2 ambient.

Ultrathin Gate Dielectric Growth at Reduced Pressure

1994 ◽  
Vol 342 ◽  
Author(s):  
Robert McIntosh ◽  
Carl Galewski ◽  
John Grant
Keyword(s):  
Gate Dielectric ◽  
Charge Trapping ◽  
Cmos Technology ◽  
Interface State ◽  
Constant Current ◽  
Reduced Pressure ◽  
Current Stress ◽  
Ultrathin Oxides ◽  
State Generation ◽  
Improved Characteristics

The Growth of ultrathin oxides in N2O ambient has been a subject of extensive research for submicron CMOS technology. Oxides grown in N2O tend to have a higher charge-to-breakdown, less charge trapping under constant current stress, and less interface state generation under current stress and radiation than conventional oxides grown in oxygen [1,2]. In addition the penetration of boron through N2O oxides is significantly less than through conventional thermal oxides [3]. The improved characteristics of N2O are due to an interfacial pileup of nitrogen atoms [1-3]. Thus the growth of thermal oxides in N2O provides a method for obtaining many of the more favorable aspects of reoxidized-nitrided silicon dioxides, with a much simpler process.

Low Temperature (850 °C) Two-Step N2O Annealed Thin Gate Oxides

1996 ◽  
Vol 428 ◽  
Author(s):  
Chao Sung Lai ◽  
Chung Len Lee ◽  
Tan Fu Lei ◽  
Tien Sheng Chao ◽  
Chun Hung Peng ◽  
...  
Keyword(s):  
Low Temperature ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Charge Trapping ◽  
Interface State ◽  
Constant Current ◽  
Short Channel ◽  
Gate Oxides ◽  
Current Stressing ◽  
State Generation

AbstractThe electrical characteristics of thin gate dielectrics prepared by low temperature (850 °C) two-step N20 nitridation (LTN) process are presented. The gate oxides were grown by wet oxidation at 800 °C and then annealed in N2O at 850 °C. The oxide with N2O anneal, even for low temperature (850 °C), had nitrogen incorporation at oxide/silicon interface. The charge trapping phenomena and interface-state generation (ΔDitm) induced by constant current stressing were reduced and charge-to-breakdown (Qbd) under constant current stressing was increased. This LTN oxynitride was used as gate dielectric for N-channel MOSFET, whose hot-canrier immunity was shown improved and reverse short channel effect (RSCE) was suppressed.

Characteristics of Thin Layers of SiO2 Fabricated by Rapid Thermal Oxidation

1987 ◽  
Vol 92 ◽  
Author(s):  
S. Prasad ◽  
J. Haase ◽  
R. Früchtnicht ◽  
R. Ferretti ◽  
D. Haack
Keyword(s):  
Growth Rate ◽  
Thermal Oxidation ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Thin Layers ◽  
Rapid Thermal Oxidation ◽  
High Temperature Anneal ◽  
Work Function Difference ◽  
Function Difference

ABSTRACTThin layers of SiO2 (60-300 Å) were fabricated by rapid thermal oxidation (RTO). Growth rate on (100) and (111) Si was determined. Two different high-temperature anneal cycles were used to reduce the interface state density. Work function difference between metal and semiconductor depends upon technology and can be attributed to the changes in Si-SiO2 barrier height.

High Quality Ultrathin Gate Dielectrics Prepared by In-Situ RTP

1995 ◽  
Vol 387 ◽  
Author(s):  
L. K. Han ◽  
M. Bhat ◽  
J. Yan ◽  
D. Wristers ◽  
D. L. Kwong
Keyword(s):  
Gate Dielectric ◽  
Defect Density ◽  
Gate Dielectrics ◽  
Charge Trapping ◽  
Interface State ◽  
High Quality ◽  
Hot Carrier ◽  
Thermal Oxide ◽  
State Generation

AbstractThis paper reports on the formation of high quality ultrathin oxynitride gate dielectric by in-situ rapid thermal multiprocessing. Four such gate dielectrics are discussed here; (i) in-situ NO-annealed SiO2, (ii) N2O- or NO- or O2-grown bottom oxide/RTCVD SiO2/thermal oxide, (iii) N2O-grown bottom oxide/Si3N4/N2O-oxide (ONO) and (iv) N2O-grown bottom oxide/RTCVD SiO2/N2O-oxide. Results show that capacitors with NO-based oxynitride gate dielectrics, stacked oxynitride gate dielectrics with varying quality of bottom oxide (O2/N2O/NO), and the ONO structures show high endurance to interface degradation, low defect-density and high charge-to-breakdown compared to thermal oxide. The N2O-last reoxidation step used in the stacked dielectrics and ONO structures is seen to suppress charge trapping and interface state generation under Fowler-Nordheim injection. The stacked oxynitride gate dielectrics also show excellent MOSFET performance in terms of transconductance and mobility. While the current drivability and mobilities are found to be comparable to thermal oxide for N-channel MOSFET's, the hot-carrier immunity of N-channel MOSFET's with the N2O-oxide/CVD-SiO2/N2O-oxide gate dielectrics is found to be significantly enhanced over that of conventional thermal oxide.

Effect of Growth Conditions on the Reliability of Ultrathin MOS Gate Oxides

1996 ◽  
Vol 428 ◽  
Author(s):  
Tien-Chun Yang ◽  
Krishna C. Saraswat
Keyword(s):  
Gate Oxide ◽  
Interface State ◽  
Growth Conditions ◽  
Physical Stress ◽  
Constant Current ◽  
Strong Function ◽  
Oxidation Rates ◽  
Mos Devices ◽  
State Generation ◽  
Mos Gate

AbstractIn this work we demonstrate that in MOS devices the reliability of ultrathin (< 100Å) gate oxide is a strong function of growth conditions, such as, temperature and the growth rate. In addition, for constant current gate injection the degradation of SiO2 is enhanced as the thickness is reduced. We attribute this to physical stress in SiO2 resulting from the growth process. The degradation is always more for those growth conditions which result in higher physical stress in SiO2. Higher temperatures and slower oxidation rates allow stress relaxation through viscous flow and hence result in SiO2 of better reliability. We also found that for constant current stressing, the interface damage is more at the collecting electrode than at the injecting electrode. ΔDit (stress induced interface state generation) can be reduced after a high temperature Ar post anneal after the gate oxide growth.

Gate Oxynitride Grown in N2O and Annealed in NO Using Rapid Thermal Processing

1995 ◽  
Vol 387 ◽  
Author(s):  
S. C. Sun ◽  
C. H. Chen ◽  
J. C. Lou ◽  
L. W. Yen ◽  
C. J. Lin
Keyword(s):  
Gate Dielectrics ◽  
Charge Trapping ◽  
Oxide Thickness ◽  
Interface State ◽  
No Oxidation ◽  
Nitrogen Accumulation ◽  
Electrical Stress ◽  
Wide Range ◽  
State Generation ◽  
Stress Induced Leakage Current

AbstractIn this paper a new technique for the formation of high quality ultrathin gate dielectrics is proposed. Gate oxynitride was first grown in N2O and then annealed by in-situ rapid thermal NO-nitridation. This approach has the advantage of providing a tighter nitrogen distribution and a higher nitrogen accumulation at or near the Si-SiO2 interface than either N2O oxynitride or nitridation of SiO2 in the NO ambient. It is applicable to a wide range of oxide thickness because the initial rapid thermal N2O oxidation rate is slow but not as self-limited as NO oxidation. The resulting gate dielectrics have reduced charge trapping, lower stress-induced leakage current and significant resistance to interface state generation under electrical stress

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