Low Temperature (850 °C) Two-Step N2O Annealed Thin Gate Oxides

1996 ◽  
Vol 428 ◽  
Author(s):  
Chao Sung Lai ◽  
Chung Len Lee ◽  
Tan Fu Lei ◽  
Tien Sheng Chao ◽  
Chun Hung Peng ◽  
...  
Keyword(s):  
Low Temperature ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Charge Trapping ◽  
Interface State ◽  
Constant Current ◽  
Short Channel ◽  
Gate Oxides ◽  
Current Stressing ◽  
State Generation

AbstractThe electrical characteristics of thin gate dielectrics prepared by low temperature (850 °C) two-step N20 nitridation (LTN) process are presented. The gate oxides were grown by wet oxidation at 800 °C and then annealed in N2O at 850 °C. The oxide with N2O anneal, even for low temperature (850 °C), had nitrogen incorporation at oxide/silicon interface. The charge trapping phenomena and interface-state generation (ΔDitm) induced by constant current stressing were reduced and charge-to-breakdown (Qbd) under constant current stressing was increased. This LTN oxynitride was used as gate dielectric for N-channel MOSFET, whose hot-canrier immunity was shown improved and reverse short channel effect (RSCE) was suppressed.

Ultrathin Gate Dielectric Growth at Reduced Pressure

1994 ◽  
Vol 342 ◽  
Author(s):  
Robert McIntosh ◽  
Carl Galewski ◽  
John Grant
Keyword(s):  
Gate Dielectric ◽  
Charge Trapping ◽  
Cmos Technology ◽  
Interface State ◽  
Constant Current ◽  
Reduced Pressure ◽  
Current Stress ◽  
Ultrathin Oxides ◽  
State Generation ◽  
Improved Characteristics

The Growth of ultrathin oxides in N2O ambient has been a subject of extensive research for submicron CMOS technology. Oxides grown in N2O tend to have a higher charge-to-breakdown, less charge trapping under constant current stress, and less interface state generation under current stress and radiation than conventional oxides grown in oxygen [1,2]. In addition the penetration of boron through N2O oxides is significantly less than through conventional thermal oxides [3]. The improved characteristics of N2O are due to an interfacial pileup of nitrogen atoms [1-3]. Thus the growth of thermal oxides in N2O provides a method for obtaining many of the more favorable aspects of reoxidized-nitrided silicon dioxides, with a much simpler process.

High Quality Ultrathin Gate Dielectrics Prepared by In-Situ RTP

1995 ◽  
Vol 387 ◽  
Author(s):  
L. K. Han ◽  
M. Bhat ◽  
J. Yan ◽  
D. Wristers ◽  
D. L. Kwong
Keyword(s):  
Gate Dielectric ◽  
Defect Density ◽  
Gate Dielectrics ◽  
Charge Trapping ◽  
Interface State ◽  
High Quality ◽  
Hot Carrier ◽  
Thermal Oxide ◽  
State Generation

AbstractThis paper reports on the formation of high quality ultrathin oxynitride gate dielectric by in-situ rapid thermal multiprocessing. Four such gate dielectrics are discussed here; (i) in-situ NO-annealed SiO2, (ii) N2O- or NO- or O2-grown bottom oxide/RTCVD SiO2/thermal oxide, (iii) N2O-grown bottom oxide/Si3N4/N2O-oxide (ONO) and (iv) N2O-grown bottom oxide/RTCVD SiO2/N2O-oxide. Results show that capacitors with NO-based oxynitride gate dielectrics, stacked oxynitride gate dielectrics with varying quality of bottom oxide (O2/N2O/NO), and the ONO structures show high endurance to interface degradation, low defect-density and high charge-to-breakdown compared to thermal oxide. The N2O-last reoxidation step used in the stacked dielectrics and ONO structures is seen to suppress charge trapping and interface state generation under Fowler-Nordheim injection. The stacked oxynitride gate dielectrics also show excellent MOSFET performance in terms of transconductance and mobility. While the current drivability and mobilities are found to be comparable to thermal oxide for N-channel MOSFET's, the hot-carrier immunity of N-channel MOSFET's with the N2O-oxide/CVD-SiO2/N2O-oxide gate dielectrics is found to be significantly enhanced over that of conventional thermal oxide.

Rapid Thermal Oxidation of Lightly Doped Silicon in N2O

1994 ◽  
Vol 342 ◽  
Author(s):  
S.C. Sun ◽  
L.S. Wang ◽  
F.L. Yeh ◽  
T.S. Lai ◽  
Y.H. Lin
Keyword(s):  
Growth Rate ◽  
Thermal Oxidation ◽  
Charge Trapping ◽  
Interface State ◽  
Constant Current ◽  
Mos Capacitor ◽  
Rapid Thermal Oxidation ◽  
Doped Silicon ◽  
State Generation ◽  
First Time

ABSTRACTIn this paper, a detailed study is presented for the growth kinetics of rapid thermal oxidation of lightly-doped silicon in N2O and O2 on (100), (110), and (111) oriented substrates. It was found that (110)-oriented Si has the highest growth rate in both N2O and dry O2, and (100) Si has the lowest rate. There is no “crossover” on the growth rate of rapid thermal N2O oxidation between (110) Si and (111) Si as compared to oxides grown in furnace N2O. Pressure dependence of rapid thermal N2O oxidation is reported for the first time. MOS capacitor results show that the low-pressure (40 Torr) N2O-grown oxides have much less interface state generation and charge trapping under constant current stress as compared to oxides grown in either 760 Torr N2O or O2 ambient.

Gate Oxynitride Grown in N2O and Annealed in NO Using Rapid Thermal Processing

1995 ◽  
Vol 387 ◽  
Author(s):  
S. C. Sun ◽  
C. H. Chen ◽  
J. C. Lou ◽  
L. W. Yen ◽  
C. J. Lin
Keyword(s):  
Gate Dielectrics ◽  
Charge Trapping ◽  
Oxide Thickness ◽  
Interface State ◽  
No Oxidation ◽  
Nitrogen Accumulation ◽  
Electrical Stress ◽  
Wide Range ◽  
State Generation ◽  
Stress Induced Leakage Current

AbstractIn this paper a new technique for the formation of high quality ultrathin gate dielectrics is proposed. Gate oxynitride was first grown in N2O and then annealed by in-situ rapid thermal NO-nitridation. This approach has the advantage of providing a tighter nitrogen distribution and a higher nitrogen accumulation at or near the Si-SiO2 interface than either N2O oxynitride or nitridation of SiO2 in the NO ambient. It is applicable to a wide range of oxide thickness because the initial rapid thermal N2O oxidation rate is slow but not as self-limited as NO oxidation. The resulting gate dielectrics have reduced charge trapping, lower stress-induced leakage current and significant resistance to interface state generation under electrical stress

Ultra-thin Gate Oxide Prepared by Nitridation in ND3 for MOS Device Applications

2000 ◽  
Vol 611 ◽  
Author(s):  
Hyungshin Kwon ◽  
Hyunsang Hwang
Keyword(s):  
Gate Dielectric ◽  
Charge Trapping ◽  
Gate Oxide ◽  
Interface State ◽  
Nitridation Process ◽  
Reliability Characteristics ◽  
State Generation ◽  
Device Applications ◽  
Thin Gate Oxide ◽  
Mos Device

ABSTRACTThe electrical and reliability characteristics of ultra-thin gate oxide, annealed in ND3 gas, have been investigated. Compared with a control oxide, which had been annealed in NH3, the ND3-nitrided oxide exhibits a significant reduction in charge trapping and interface state generation. The improvement of electrical and reliability characteristics can be explained by the strong Si-D bond at the Si/SiO2 interface. This nitridation process of gate dielectric using ND3 has considerable potential for future ultra large scaled integration (ULSI) device applications.

Charge trapping and polarity dependence of interface state generation in nitrided oxide gate dielectric by electron photoinjection

1994 ◽  
Vol 30 (14) ◽  
pp. 1180-1181
Author(s):  
X.-J. Yuan ◽  
W. Eccleston ◽  
J. Mi ◽  
J.S. Marsland ◽  
D. Bouvet ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Charge Trapping ◽  
Interface State ◽  
State Generation

TMCTS for gate dielectric in thin film transistors

1996 ◽  
Vol 424 ◽  
Author(s):  
Albert W. Wang ◽  
Navakanta Bhat ◽  
Krishna C. Saraswat
Keyword(s):  
Thin Film ◽  
Low Temperature ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Thin Film Transistor ◽  
Superior Performance ◽  
Stress Tests ◽  
Gate Oxides ◽  
Liquid Source ◽  
Temperature Oxide

AbstractThe use of the liquid source tetramethylcyclotetrasiloxane (TMCTS) for gate dielectric deposition in low-temperature polysilicon thin film transistor (TFT) processes is investigated. TMCTS was reacted with O2 in an LPCVD furnace at 580°C to form a gate dielectric. For comparison, a low temperature oxide (LTO) was deposited as a gate dielectric using SiH4−O2 LPCVD at 450°C. Capacitance and charge pumping measurements indicate fewer interface states for TMCTS gate dielectric. Both NMOS and PMOS TFTs show comparable or superior performance with TMCTS oxide. Post-deposition annealing has less effect on TMCTS gate oxides. Although TMCTS gate dielectrics appear slightly more susceptible to damage in biastemperature stress tests, TFTs with TMCTS gate oxides still retain better performance after stressing.

Effect of Technology Scaling on MOS Transistor Performance with High-K Gate Dielectrics

2002 ◽  
Vol 716 ◽  
Author(s):  
Nihar R. Mohapatra ◽  
Madhav P. Desai ◽  
Siva G. Narendra ◽  
V. Ramgopal Rao
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Channel Length ◽  
Mos Transistors ◽  
Short Channel ◽  
Technology Scaling ◽  
Mos Transistor ◽  
Wide Range ◽  
Impact Of Technology ◽  
The Impact

AbstractThe impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations.

scholarly journals Demonstration of AlGaN/GaN MISHEMT on Si with Low-Temperature Epitaxy Grown AlN Dielectric Gate

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1858
Author(s):  
Matthew Whiteside ◽  
Subramaniam Arulkumaran ◽  
Yilmaz Dikme ◽  
Abhinay Sandupatla ◽  
Geok Ing Ng
Keyword(s):  
Low Temperature ◽  
Gate Dielectric ◽  
Drain Current ◽  
High Electron Mobility Transistors ◽  
Interface State ◽  
State Density ◽  
High Electron ◽  
Gate Leakage ◽  
Annealing Effects ◽  
Low Temperature Epitaxy

AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MISHEMT) with a low-temperature epitaxy (LTE)-grown single crystalline AlN gate dielectric were demonstrated for the first time and the post-gate annealing effects at 400 °C were studied. The as-deposited LTE-AlN MISHEMT showed a maximum drain current (IDmax) of 708 mA/mm at a gate bias of 4 V and a maximum extrinsic transconductance (gmmax) of 129 mS/mm. The 400 °C annealed MISHEMT exhibited an increase of 15% in gmmax, an order of magnitude reduction in reverse gate leakage and about a 3% suppression of drain current (ID) collapse. The increase of gmmax by post-gate annealing is consistent with the increase of 2DEG mobility. The suppression of ID collapse and the reduction of gate leakage current is attributed to the reduction of interface state density (5.0 × 1011 cm−2eV−1) between the AlN/GaN interface after post-gate annealing at 400 °C. This study demonstrates that LTE grown AlN is a promising alternate material as gate dielectric for GaN-based MISHEMT application.

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