Electrical Properties of Stacked RTO/RTCVD Oxides as Gate Dielectrics

1994 ◽  
Vol 342 ◽  
Author(s):  
V. Misra ◽  
X-L. Xu ◽  
J.J. Wortman
Keyword(s):  
Gate Dielectric ◽  
Defect Density ◽  
Gate Dielectrics ◽  
Electrical Characterization ◽  
Single Layer ◽  
Superior Performance ◽  
Potential Candidate ◽  
Thermal Budget ◽  
Thermal Oxide

ABSTRACTTo meet the stringent demands of high quality gate performance in advanced devices, a more robust gate dielectric is needed. A stacked structure consisting of thermal oxide and deposited oxide is a potential candidate since it offers certain advantages over single layer oxides such as 1) reduced defect density, 2) reduced stress at the SiO2/Si interface due to stress compensation between the thermal and the deposited oxide, 3) less silicon consumption and 4) reduced thermal budget. In this study, stacked oxides consisting of RTO and RTCVD oxides are characterized. In contrast to other studies which use conventional LPCVD methods to form the top oxide, these stacked oxides have the advantages of rapid thermal and in-situ processing, which produces excellent bulk and interfacial properties. Electrical characterization has shown that these stacked oxides have superior performance compared to single layer furnace or deposited oxides.

High Quality Ultrathin Gate Dielectrics Prepared by In-Situ RTP

1995 ◽  
Vol 387 ◽  
Author(s):  
L. K. Han ◽  
M. Bhat ◽  
J. Yan ◽  
D. Wristers ◽  
D. L. Kwong
Keyword(s):  
Gate Dielectric ◽  
Defect Density ◽  
Gate Dielectrics ◽  
Charge Trapping ◽  
Interface State ◽  
High Quality ◽  
Hot Carrier ◽  
Thermal Oxide ◽  
State Generation

AbstractThis paper reports on the formation of high quality ultrathin oxynitride gate dielectric by in-situ rapid thermal multiprocessing. Four such gate dielectrics are discussed here; (i) in-situ NO-annealed SiO2, (ii) N2O- or NO- or O2-grown bottom oxide/RTCVD SiO2/thermal oxide, (iii) N2O-grown bottom oxide/Si3N4/N2O-oxide (ONO) and (iv) N2O-grown bottom oxide/RTCVD SiO2/N2O-oxide. Results show that capacitors with NO-based oxynitride gate dielectrics, stacked oxynitride gate dielectrics with varying quality of bottom oxide (O2/N2O/NO), and the ONO structures show high endurance to interface degradation, low defect-density and high charge-to-breakdown compared to thermal oxide. The N2O-last reoxidation step used in the stacked dielectrics and ONO structures is seen to suppress charge trapping and interface state generation under Fowler-Nordheim injection. The stacked oxynitride gate dielectrics also show excellent MOSFET performance in terms of transconductance and mobility. While the current drivability and mobilities are found to be comparable to thermal oxide for N-channel MOSFET's, the hot-carrier immunity of N-channel MOSFET's with the N2O-oxide/CVD-SiO2/N2O-oxide gate dielectrics is found to be significantly enhanced over that of conventional thermal oxide.

Evaluation Of 2.0 nm Grown and Deposited Dielectrics in 0.1 μm PMOSFETs

1998 ◽  
Vol 525 ◽  
Author(s):  
A. Srivastava ◽  
H. H. Heinisch ◽  
E. Vogel ◽  
C. Parker ◽  
C. M. Osburn ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Electrical Characterization ◽  
Deposition Process ◽  
Gate Oxides ◽  
Boron Doped ◽  
Excellent Control ◽  
Lower Temperature ◽  
Boron Penetration

ABSTRACTThe quality and composition of ultra-thin 2.0 nm gate dielectrics advocated for the 0.1 μm technology regime is expected to significantly impact gate tunneling currents, P+-gate dopant depletion effects and boron penetration into the substrate in PMOSFETs. This paper presents a comparative assessment of alternative grown and deposited gate dielectrics in sub-micron fabricated devices. High quality rapid-thermal CVD oxides and oxynitrides are examined as alternatives to conventional furnace grown gate oxides. An alternative gate process using in-situ boron doped and RTCVD deposited poly-Si is explored. PMOSFETs with Leff down to 0.06 μm were fabricated using a 0.1 μm technology. Electrical characterization of fabricated devices revealed excellent control of gate-boron depletion with the in-situ gate deposition process in all devices. Boron penetration of 2.0 nm gate oxides was effectively controlled by the use of a lower temperature RTA process. The direct tunneling leakage, although significant at these thicknesses, was less than 1 mA/cm2 at Vd = −1.2 V for all dielectrics. MOSFETs with comparable drive currents and excellent junction and off-state leakages were obtained with each dielectric.

Fabrication and Characterization of Directly-Assembled ZnO Nanowire Field Effect Transistors with Polymer Gate Dielectrics

2007 ◽  
Vol 7 (11) ◽  
pp. 4101-4105
Author(s):  
Ahnsook Yoon ◽  
Woong-Ki Hong ◽  
Takhee Lee
Keyword(s):  
Dielectric Layer ◽  
Field Effect ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Field Effect Transistors ◽  
Electrical Characterization ◽  
Electrical Characteristics ◽  
Zno Nanowire ◽  
Device Structure

We report the fabrication and electrical characterization of ZnO nanowire field effect transistors (FETs). Dielectrophoresis technique was used to directly align ZnO nanowires between lithographically prepatterned source and drain electrodes, and spin-coated polyvinylphenol (PVP) polymer thin layer was used as a gate dielectric layer in "top-gate" FET device configuration. The electrical characteristics of the top-gate ZnO nanowire FETs were found to be comparable to the conventional "bottom-gate" nanowire FETs with a SiO2 gate dielectric layer, suggesting the directly-assembled nanowire FET with a polymer gate dielectric layer is a useful device structure of nanowire FETs.

scholarly journals Electrical Characteristics and Stability Improvement of Top-Gate In-Ga-Zn-O Thin-Film Transistors with Al2O3/TEOS Oxide Gate Dielectrics

Coatings ◽  
2020 ◽  
Vol 10 (12) ◽  
pp. 1146
Author(s):  
Yih-Shing Lee ◽  
Yu-Hsin Wang ◽  
Tsung-Cheng Tien ◽  
Tsung-Eong Hsieh ◽  
Chun-Hung Lai
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Single Layer ◽  
Charge Trapping ◽  
Indium Gallium Zinc Oxide ◽  
Electrical Characteristics ◽  
Electrical Stability ◽  
Bias Stress

In this work, two stacked gate dielectrics of Al2O3/tetraethyl-orthosilicate (TEOS) oxide were deposited by using the equivalent capacitance with 100-nm thick TEOS oxide on the patterned InGaZnO layers to evaluate the electrical characteristics and stability improvement of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) devices, including positive bias stress (PBS) and negative bias stress (NBS) tests. Three different kinds of gate dielectrics (Al2O3, TEOS, Al2O3/TEOS) were used to fabricate four types of devices, differing by the gate dielectric, as well as its thickness. As the Al2O3 thickness of Al2O3/TEOS oxide dielectric stacks increased, both the on-current and off-current decreased, and the transfer curves shifted to larger voltages. The lowest ∆Vth of 0.68 V and ∆S.S. of −0.03 V/decade from hysteresis characteristics indicate that the increase of interface traps and charge trapping between the IGZO channel and gate dielectrics is effectively inhibited by using two stacked dielectrics with 10-nm thick Al2O3 and 96-nm thick TEOS oxide. The lowest ∆Vth and ∆S.S. values of a-IGZO TFTs with 10-nm thick Al2O3 and 96-nm thick TEOS oxide gate dielectrics according to the PBS and NBS tests were shown to have the best electrical stability in comparison to those with the Al2O3 or TEOS oxide single-layer dielectrics.

Electrical Characterization of MOS Structures with Silicon Nanocrystals Suitable for X-Ray Detection

2013 ◽  
Vol 543 ◽  
pp. 150-153
Author(s):  
David Mateos ◽  
Nicola Nedev ◽  
Diana Nesheva ◽  
Mario Curiel ◽  
Emil Manolov ◽  
...  
Keyword(s):  
Silicon Nanocrystals ◽  
Gate Dielectric ◽  
Defect Density ◽  
Electrical Characterization ◽  
Oxide Semiconductor ◽  
Electrical Measurements ◽  
Transmission Electron ◽  
Interface Defect ◽  
Mos Structures

Metal-Oxide-Semiconductor structures with silicon nanocrystals in the oxide layer are prepared and characterized by Transmission Electron Microscopy and electrical measurements. High temperature annealing of SiO1.15 films at 1000 °C for 30 or 60 min leads to formation of silicon nanocrystals with diameters of 2-3 or 4-6 nm. The processes used to obtain the multilayer gate dielectric and to grow nanocrystals do not deteriorate the properties of the cSi wafer/thermal SiO2 interface. For the interface defect density and the fixed oxide charge values 1010 cm-2 eV-1 and ~ 1010 cm-2 were obtained.

Performance and Reliability of thin Gate Dielectrics for VLSI: Materials and Processing Perspective

1986 ◽  
Vol 71 ◽  
Author(s):  
R. Singh
Keyword(s):  
Dielectric Constant ◽  
High Dielectric Constant ◽  
Gate Dielectric ◽  
Dielectric Material ◽  
Gate Dielectrics ◽  
Current Trends ◽  
High Dielectric ◽  
Rapid Isothermal Processing ◽  
Gate Dielectric Material

AbstractCurrent trends are in the direction of submicron MOSFETs employing gate dielectrics in the thickness range of about 30 - 100A°. The performance and reliability of submicron MOSFETs can be improved by using high dielectric constant gate dielectric material. A new concept involving 2 or more dielectric material is proposed in this paper. In- situ rapid isothermal processing is proposed for the fabrication of thin gate dielectrics.

Fabrication and Characterization of Directly-Assembled ZnO Nanowire Field Effect Transistors with Polymer Gate Dielectrics

2007 ◽  
Vol 7 (11) ◽  
pp. 4101-4105 ◽  
Author(s):  
Ahnsook Yoon ◽  
Woong-Ki Hong ◽  
Takhee Lee
Keyword(s):  
Dielectric Layer ◽  
Field Effect ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Field Effect Transistors ◽  
Electrical Characterization ◽  
Electrical Characteristics ◽  
Zno Nanowire ◽  
Device Structure

We report the fabrication and electrical characterization of ZnO nanowire field effect transistors (FETs). Dielectrophoresis technique was used to directly align ZnO nanowires between lithographically prepatterned source and drain electrodes, and spin-coated polyvinylphenol (PVP) polymer thin layer was used as a gate dielectric layer in "top-gate" FET device configuration. The electrical characteristics of the top-gate ZnO nanowire FETs were found to be comparable to the conventional "bottom-gate" nanowire FETs with a SiO2 gate dielectric layer, suggesting the directly-assembled nanowire FET with a polymer gate dielectric layer is a useful device structure of nanowire FETs.

Ultra-Thin Zirconium Silicate Filmsc With Good Physical And Electrical Properties For Gate Dielectric Applications

2000 ◽  
Vol 648 ◽  
Author(s):  
Easwar Dharmarajan ◽  
Wen-Jie Qi ◽  
Renee Nieh ◽  
Laegu Kang ◽  
Katsunori Onishi ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Electrical Characterization ◽  
Oxide Thickness ◽  
Equivalent Oxide Thickness ◽  
Interface Quality ◽  
Good Thermal Stability ◽  
Cmos Scaling ◽  
Zirconium Silicate

AbstractThe need for alternative gate dielectrics to replace conventional SiO2 is increasing to facilitate further CMOS scaling. One of the most promising materials for use as an alternative gate dielectric is Zr silicate due to its thermodynamic stability on Si and its good interface quality with Si. In this study, ultra-thin Zr silicate films (45 – 60 Å thick) with different Zr compositions have been deposited on Si using magnetron reactive co-sputtering. The Zr composition was kept below the stoichiometric value of about 16% to prevent precipitation of ZrO2and to have Si rich films for better interface quality. Films were rapid thermal annealed in N2 ambient up to 9000C and Pt was used as the gate electrode. Electrical characterization of these films was done using HP 4156 and HP 4194 parameter analyzers. Based on these studies, we demonstrate Zr silicate films with equivalent oxide thickness (EOT) of less than 14 Å with gate leakage significantly lower thanSiO2 of similar thickness and hysteresis of < 20mV ( in a sweep from –3 to 3 V). The films exhibit good thermal stability on Si even after 900 0C annealing as shown by a minimal increase in EOT with annealing. TEM and XPS analyses show high quality Zr silicate films that remain stable and amorphous even at 900 0C.

Deposition and Treatment of TiO2 as an Alternative for Ultrathin Gate Dielectrics

1999 ◽  
Vol 567 ◽  
Author(s):  
Yanjun Ma ◽  
Yoshi Ono ◽  
Sheng Teng Hsu
Keyword(s):  
Leakage Current ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Desirable Property ◽  
Post Deposition Annealing ◽  
Plasma Exposure ◽  
Thermal Budget ◽  
Gate Electrodes ◽  
Post Deposition

ABSTRACTWe investigated the use of TiO2 as an alternate gate dielectric for future CMOS applications. To reduce the leakage current, different post deposition treatments were investigated. It was found that for very thin TiO2 films, ozone plasma exposure is an effective way in lowering thermal budget of the post deposition annealing. Doping TiO2with Si and/or Al can also be effective in substantially reducing the leakage current. In addition, the doped TiO2 has the desirable property of remaining amorphous even after anneal at 850°C. We also report the fabrication of submicron MOSFETs with TiO2 gate dielectrics equivalent to 2 nm of SiO2 and TiN/Cu gate electrodes.

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