Residual Gases and Their Influence on Processes in the Atmospheric Rapid Thermal Processing Equipment

1998 ◽  
Vol 525 ◽  
Author(s):  
Yao Zhi Hu ◽  
Sing Pin Tay
Keyword(s):  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Oxide Thickness ◽  
Tank Model ◽  
Process Gas ◽  
Oxygen Analyzer ◽  
Gas Purging ◽  
Flow Rate Range ◽  
Residual Gas

ABSTRACTThe residual impurity gases in the atmospheric rapid thermal processing (RTP) equipment are becoming an important factor in sub-micron ULSI industry. For example, 1% nitrogen in oxygen decreases the RT oxide thickness, and a small amount of moisture or oxygen in nitrogen may strongly affect the RT titanium silicidation. The effective method to reduce the residual gases is to use process gas to purge the chamber. In the present paper the gas purging mechanisms were in-situ investigated in the flow rate range of 10 to 60 slpm using a Quadrapole Residual Gas Analyser (RGA) and gas sensors. The gases for purging studies are N2, O2, He and Ar. It has been found that there are two regimes in the dependence of the residual gas concentration on purging time. Based on the results of systematic experiments, a purging equation, called Pseudo-PST (“perfectly stirred tank) model, has been developed and was used to give the interpretation of the purging process in the atmospheric RTP system. The limitation of the RGA and the oxygen analyzer used to atmospheric RTP system was also discussed.

Optimization of Process Parameter and Temperature Uniformity On Wafers For Rapid Thermal Processing

1995 ◽  
Vol 387 ◽  
Author(s):  
Andreas Tillmann
Keyword(s):  
Standard Deviation ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Oxide Thickness ◽  
Simulation Software ◽  
Process Parameter ◽  
Parameter Distribution ◽  
Temperature Uniformity ◽  
New Strategy ◽  
The Impact

AbstractA new strategy based algorithm to optimize process parameter uniformity (e.g.sheet resistance, oxide thickness) and temperature uniformity on wafers in a commercially available Rapid Thermal Processing (RTP) system with independent lamp control is described. The computational algorithm uses an effective strategy to minimize the standard deviation of the considered parameter distribution. It is based on simulation software which is able to calculate the temperature and resulting parameter distribution on the wafer for a given lamp correction table. A cyclical variation of the correction values of all lamps is done while minimizing the standard deviation of the considered process parameter. After the input of experimentally obtained wafer maps the optimization can be done within a few minutes. This technique is an effective tool for the process engineer to use to quickly optimize the homogeneity of the RTP tool for particular process requirements. The methodology will be shown on the basis of three typical RTP applications (Rapid Thermal Oxidation, Titanium Silicidation and Implant Annealing). The impact of variations of correction values for single lamps on the resulting process uniformity for different applications will be discussed.

Rapid Thermal Annealing and Oxidation of Silicon Wafers with Back-Side Films

1997 ◽  
Vol 470 ◽  
Author(s):  
A. T. Fiory
Keyword(s):  
Thermal Oxidation ◽  
Sheet Resistance ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Temperature Control ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Oxide Thickness ◽  
Back Side ◽  
Control Accuracy

ABSTRACTTemperatures for lamp-heated rapid thermal processing of wafers with various back-side films were controlled by a Lucent Technologies pyrometer which uses a/c lamp ripple to compensate for emissivity. Process temperatures for anneals of arsenic and boron implants were inferred from post-anneal sheet resistance, and for rapid thermal oxidation, from oxide thickness. Results imply temperature control accuracy of 12°C to 17°C at 3 standard deviations.

Temperature Monitoring by Ripple Pyrometry in Rapid Thermal Processing

1996 ◽  
Vol 429 ◽  
Author(s):  
Binh Nguyenphu ◽  
Minseok Oh ◽  
Anthony T. Fiory
Keyword(s):  
Temperature Control ◽  
Integrated Circuit ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Back Side ◽  
Integrated Circuit Manufacturing ◽  
Current Trends ◽  
Processing Steps ◽  
Electrical Data

AbstractCurrent trends of silicon integrated circuit manufacturing demand better temperature control in various thermal processing steps. Rapid thermal processing (RTP) has become a key technique because its single wafer process can accommodate the reduced thermal budget requirements arising from shrinking the dimensions of devices and the trend to larger wafers. However, temperature control by conventional infrared pyrometry, which is highly dependent on wafer back side conditions, is insufficiently accurate for upcoming technologies. Lucent Technologies Inc., formerly known as AT&T Microelectronics and AT&T Bell Laboratories, has developed a powerful real-time pyrometry technique using the A/C ripple signal from heating lamps for in-situ temperature measurement. Temperature and electrical data from device wafers have been passively collected by ripple pyrometers in three RTP systems and analyzed. In this paper we report the statistical analysis of ripple temperature and electrical data from device wafers for a typical implant anneal process temperature range of 900 to 1000 °C.

Polysilicon Emitter Transistors Manufactured using a Novel Limited Reaction Processing System

1989 ◽  
Vol 146 ◽  
Author(s):  
Fred Ruddell ◽  
Colin Parkes ◽  
B Mervyn Armstrong ◽  
Harold S Gamble
Keyword(s):  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Processing System ◽  
Bipolar Transistors ◽  
Native Oxide ◽  
Plasma Oxidation ◽  
Oxide Removal ◽  
Polysilicon Emitter ◽  
Reaction Processing

ABSTRACTThis paper describes a LPCVD reactor which was developed for multiple sequential in-situ processing. The system is capable of rapid thermal processing in the presence of plasma stimulation and has been used for native oxide removal, plasma oxidation and silicon deposition. Polysilicon layers produced by the system are incorporated into N-P-N polysilicon emitter bipolar transistors. These devices fabricated using a sequential in-situ plasma clean-polysilicon deposition schedule exhibited uniform gains limited to that of long single crystal emitters. Devices with either plasma grown or native oxide layers below the polysilicon exhibited much higher gains. The suitability of the system for sequential and limited reaction processing has been established.

Rapid thermal processing chamber for in-situ x-ray diffraction

2015 ◽  
Vol 86 (1) ◽  
pp. 013902 ◽  
Author(s):  
Md. Imteyaz Ahmad ◽  
Douglas G. Van Campen ◽  
Jeremy D. Fields ◽  
Jiafan Yu ◽  
Vanessa L. Pool ◽  
...  
Keyword(s):  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
X Ray Diffraction ◽  
X Ray

In-Situ Processing of Silicon Dielectrics by Rapid Thermal Processing: Cleaning, Growth, and Annealing

1987 ◽  
Vol 92 ◽  
Author(s):  
J. Nulman
Keyword(s):  
Thermal Processing ◽  
Silicon Surface ◽  
Rapid Thermal Processing ◽  
Oxide Growth ◽  
Surface Chemical ◽  
Native Oxides ◽  
Wafer Cleaning ◽  
In Situ Processing ◽  
Kinetics Of

ABSTRACTThe in-situ processing of silicon dielectrics by rapid thermal processing (RTP) is described. RTP includes here three basic sequentially performed processes: wafer cleaning, oxidation and annealing. The insitu cleaning allows for reduction of chemical and native oxides and silicon surface chemical polish, resulting in interface density of states as low as 5×l09 cm-2eV-1. Kinetics of oxide growth indicates an activation energy of 1.4 eV for the initial linear oxidation rate.

Ge nanocrystals in MOS-memory structures produced by molecular-beam epitaxy and rapid-thermal processing

2004 ◽  
Vol 830 ◽  
Author(s):  
A. Nylandsted Larsen ◽  
A. Kanjilal ◽  
J. Lundsgaard Hansen ◽  
P. Gaiduk ◽  
P. Normand ◽  
...  
Keyword(s):  
Molecular Beam Epitaxy ◽  
Process Parameters ◽  
Gate Voltage ◽  
Thermal Processing ◽  
Molecular Beam ◽  
Rapid Thermal Processing ◽  
Oxide Thickness ◽  
Mos Capacitors ◽  
Very High ◽  
Ge Nanocrystals

ABSTRACTA method of forming a sheet of Ge nanocrystals in a SiO2 layer based on molecular beam epitaxy (MBE) and rapid thermal processing (RTP) is presented. The method takes advantage of the very high precision by which a very thin Ge layer can be deposited by MBE. With proper choice of process parameters the nanocrystal size can be varied between ∼3 and ∼8 nm and the area-density between ∼1×1011 and ∼1×1012 dots/cm2. The tunneling oxide thickness is determined by the thickness of a thermally grown SiO2 layer, and is typically 4 nm. C-V measurements of MOS capacitors reveal hole and electron injection from the substrate into the nanocrystals. Memory windows of about 0.2 and 0.5 V for gate-voltage sweeps of 3 and 6 V, respectively, are achieved.

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