Surface and Interfacial Topography of Oxides on Si(111) With Ultra-Low Atomic Step Density

1999 ◽  
Vol 592 ◽  
Author(s):  
Antonio C. Oliver ◽  
Jack M. Blakely

ABSTRACTAtomic force microscopy has been used to study the morphology of the oxide surface and the Si-SiO2 interface after oxidation of Si(111) surfaces that are either totally free of atomic steps or have well characterized low step density. The step-free areas were formed by thermally processing a patterned Si surface in which flat areas are enclosed by a square array of ridges; flow of the atomic steps into the surrounding ridge barriers produces a regular array of step-free areas each of which can be up to ∼50µm×50µm. Arrays of widely spaced steps (e.g. 5µm) can also be produced in the step-free areas. AFM scans of the same areas were taken prior to (dry) oxidation, after oxidation, and after chemical removal of the oxide. It was found that at an oxide thickness in the 5-13nm range, the initial step structure of the underlying Si substrates is translated through the oxide to the surface after oxidation with the oxide surface being somewhat rougher than the initial substrate. Furthermore, the initial step morphology of the substrate remains at the Si-SiO2 interface after etching away the oxide by HF. The interface roughness is less than that of the oxide surface. The results suggest that the initial oxidation of silicon proceeds in a ‘layer by layer’ manner and not through a preferential step-flow oxide growth mode.

2002 ◽  
Vol 747 ◽  
Author(s):  
Antonio C. Oliver ◽  
Jack M. Blakely

ABSTRACTSurface and interface morphology may play an important role in the electrical performance of metal-oxide-semiconductor (MOS) devices with small characteristic dimensions. In previous work we showed how steps on the silicon surface influence the Si-SiO2 interface morphology and the outer oxide surface morphology following thermal oxidation [1]. The Si-SiO2 interface morphology is largely determined by the starting silicon substrate step distribution and atomic steps at the Si surface cause an inherent variation in oxide thickness after thermal oxidation. In the present study we report how roughness caused by increased interfacial step density may affect the electronic tunneling characteristics of an MOS device structure. To determine the extent to which the step morphology plays a role in the tunneling behavior of such devices, similar arrays of capacitors were fabricated on both Si surfaces with reduced step density and surfaces which had not undergone any special surface step removal treatment. The leakage currents due to tunneling for the two types of capacitors were measured and compared. Atomic steps cause an effective decrease in oxide thickness in those capacitors without reduced step density and this leads to increased leakage current.


1999 ◽  
Vol 567 ◽  
Author(s):  
Heiji Watanabe ◽  
Noriyuki Miyata ◽  
Masakazu Ichikawa

ABSTRACTLayer-by-layer oxidation of Si(111) and (001) surfaces has been studied by using scanning reflection electron microscopy (SREM). We found that SREM images reveal interfacial structures of the SiO2/Si system. Our results showed that the initial step structure of Si substrates was preserved at SiO2/Si interfaces and that interfacial steps did not move laterally during oxidation. We also observed a periodic reversal of terrace contrast in SREM images during the initial oxidation of Si(001) surfaces. These results indicate layer-by-layer oxidation of Si surfaces, which is promoted by the nucleation of nanometer-scale oxide islands at SiO2/Si interfaces. In addition, we investigated the kinetics of initial layer-by-layer oxidation of Si(001) surfaces. We found that a barrierless oxidation of the first subsurface layer, as well as oxygen chemisorption onto the top layer, occur at room temperature. The energy barrier of the second-layer oxidation was found to be 0.3 eV. The initial oxidation kinetics are discussed based on first-principles calculations. Moreover, we confirmed that the layer-by-layer oxidation of Si surfaces holds true for conventional furnace oxidation.


Author(s):  
L. Hultman ◽  
C.-H. Choi ◽  
R. Kaspi ◽  
R. Ai ◽  
S.A. Barnett

III-V semiconductor films nucleate by the Stranski-Krastanov (SK) mechanism on Si substrates. Many of the extended defects present in the films are believed to result from the island formation and coalescence stage of SK growth. We have recently shown that low (-30 eV) energy, high flux (4 ions per deposited atom), Ar ion irradiation during nucleation of III-V semiconductors on Si substrates prolongs the 1ayer-by-layer stage of SK nucleation, leading to a decrease in extended defect densities. Furthermore, the epitaxial temperature was reduced by >100°C due to ion irradiation. The effect of ion bombardment on the nucleation mechanism was explained as being due to ion-induced dissociation of three-dimensional islands and ion-enhanced surface diffusion.For the case of InAs grown at 380°C on Si(100) (11% lattice mismatch), where island formation is expected after ≤ 1 monolayer (ML) during molecular beam epitaxy (MBE), in-situ reflection high-energy electron diffraction (RHEED) showed that 28 eV Ar ion irradiation prolonged the layer-by-layer stage of SK nucleation up to 10 ML. Otherion energies maintained layer-by-layer growth to lesser thicknesses. The ion-induced change in nucleation mechanism resulted in smoother surfaces and improved the crystalline perfection of thicker films as shown by transmission electron microscopy and X-ray rocking curve studies.


1997 ◽  
Vol 473 ◽  
Author(s):  
Heng-Chih Lin ◽  
Edwin C. Kan ◽  
Toshiaki Yamanaka ◽  
Simon J. Fang ◽  
Kwame N. Eason ◽  
...  

ABSTRACTFor future CMOS GSI technology, Si/SiO2 interface micro-roughness becomes a non-negligible problem. Interface roughness causes fluctuations of the surface normal electric field, which, in turn, change the gate oxide Fowler-Nordheim tunneling behavior. In this research, we used a simple two-spheres model and a three-dimensional Laplace solver to simulate the electric field and the tunneling current in the oxide region. Our results show that both quantities are strong functions of roughness spatial wavelength, associated amplitude, and oxide thickness. We found that RMS roughness itself cannot fully characterize surface roughness and that roughness has a larger effect for thicker oxide in terms of surface electric field and tunneling behavior.


1996 ◽  
Vol 427 ◽  
Author(s):  
Hyeongtag Jeon ◽  
Sukjae Lee ◽  
Hwackjoo Lee ◽  
Hyun Ruh

AbstractTwo different Si(100) substrates, the 4°off-axis and the on-axis Si(100), were prepared. Ti thin films were deposited in an e-beam evaporation system and the amorphous layers of Ti-silicide were formed at different annealing temperatures. The Si(100) substrates before Ti film deposition were examined with AFM to verify the atomic scale roughness of the initial Si substrates. The amorphous layer was observed by HRTEM and TEM. And the chemical analysis and phase identification were examined by AES and XRD. The Si(100) substrate after HF clean shows the atomic scale microroughness such as atomic steps and pits on the Si surface. The on-axis Si(100) substrate exhibits much rougher surface morphologies than those of the off-axis Si(100). These differences of atomic scale roughnesses of Si substrates result in the difference of the thicknesses of amorphous Ti-silicide layers. The amorphous layer thicknesses on the on-axis exhibit thicker than those of the off-axis Si(100) and these differences inamorphous layer thicknesses became decreased as annealing temperatures increased. These indicate that the role of the atomic scale roughness on the amorphous layer thickness is much significant at low temperatures. In this study, the correlation between the atomic scale roughness and the amorphous layer thickness is discussed in terms of the atomic steps and pits based on the observation with using analysis tools such as AFM, TEM and HRTEM.


2011 ◽  
Vol 11 (4) ◽  
pp. 2928-2930 ◽  
Author(s):  
Takeshi Okamoto ◽  
Yasuhisa Sano ◽  
Kazuma Tachibana ◽  
Kenta Arima ◽  
Azusa N. Hattori ◽  
...  

1999 ◽  
Vol 567 ◽  
Author(s):  
K. Watanabe ◽  
S. Kimura ◽  
T. Tatsumi

ABSTRACTRadical oxidation at thickness of under 2.0 nm in an ultrahigh vacuum (UHV) system with an electron cyclotron resonance (ECR) plasma has been studied. The interface roughness and oxide density were evaluated by atomic force microscopy (AFM) and grazing incidence xray reflectrometry, respectively. We found the oxide thickness could be easily controlled at Tsub = 750°C when using radical oxygen at 5.0×10−3Torr. The interface roughness at a thickness of 1.8 nm, measured by the root mean square (RMS), was 0.11 nm. The density of the radical oxide fell as the oxide thickness decreased, especially at less than 2.0 nm. However, the density of the radical oxide annealed in molecular oxygen at 5×10−3Torr and Tsub = 750°C increased, without the oxide thickness increasing. We think that the first insertion of an oxygen atom into the first Si layer has a much higher energy barrier than that into a SiOx layer. The radical oxygen can pass through this higher energy barrier, and thus oxygen molecules fill the oxide layers. This mechanism means that we can control the oxide thickness and density separately at thickness of less than 2.0 nm through the radical oxidation time and the annealing time in molecular oxygen. We expect low-pressure radical oxidation to be the most suitable process for future ultrathin gate oxidation.


1987 ◽  
Vol 105 ◽  
Author(s):  
Kyung-Ho Park ◽  
T. Sasaki ◽  
S. Matsuoka ◽  
M. Yoshida ◽  
M. Nakano

AbstractInterfaces between two kind of substrate, a bulk silicon wafer and a laser-recrystallized Silicon-On-Insulator (SOI), and its thermally grown oxide have been studied. High resolution transmission electron microscopy (HRTEM) of cross sectional specimen shows that the roughness at the interface is atomically flat and nearly uniform for the bulk single crystal silicon and silicon oxide, while being nonuniform and rough as much as 20 nm height for the recrystallized silicon and silicon oxide interface. Consideration of interface between recrystallized silicon and silicon oxide, and the oxide surface above, the observed roughness at the interface is due to original grain boundaries of polycrystalline silicon which was used as the material for the laser recrystallized silicon formation. It is also discussed HRTEM of the interface between polycrystalline silicon and silicon oxide.


2019 ◽  
Vol 9 (1) ◽  
Author(s):  
Sergey Kosolobov

Abstract A new theoretical approach to characterize the diffusion of both surface and bulk point defects in crystals is presented. In our model, atomic steps are considered as sources and sinks not only for adatoms and advacancies but also for self-interstitials and bulk vacancies, providing a new mechanism for bulk point defect generation and annihilation. It is shown that the creation and annihilation of self-interstitials and vacancies occur at atomic steps and can be described by introducing a diffusive layer of the bulk point defects adsorbed just below the surface. The atomic step rate of advance is studied taking into account finite permeability of the surface for bulk and surface point defects. The surface permeability results in the appearance of the dependence of the total step rate of advance not only on the supersaturation in vapor phase but also on the supersaturation of point defects in the bulk.


1999 ◽  
Vol 595 ◽  
Author(s):  
P. Chen ◽  
R. Zhang ◽  
X.F. Xu ◽  
Z.Z. Chen ◽  
Y.G. Zhou ◽  
...  

AbstractThe oxidation of GaN epilayers in dry oxygen has been studied. The 1-μm-thick GaN epilayers grown on (0001) sapphire substrates by Rapid-Thermal-Processing/Low Pressure Metalorganic Chemical Vapor Deposition were used in this work. The oxidation of GaN in dry oxygen was performed at various temperatures for different time. The oxide was identified as the monoclinic β-Ga2O3 by a θ-2θ scan X-ray diffraction (XRD). The scanning electron microscope observation shows a rough oxide surface and an expansion of the volume. XRD data also showed that the oxidation of GaN began to occur at 800°C. The GaN diffraction peaks disappeared at 1050°C for 4 h or at 1100°C for 1 h, which indicates that the GaN epilayers has been completely oxidized. From these results, it was found that the oxidation of GaN in dry oxygen was not layer-by-layer and limited by the interfacial reaction and diffusion mechanism at different temperatures.


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