Integration Processes and Properties of Pt/Pb5Ge3O11/(Zr, Hf)O2/Si One Transistor Memory Devices

2001 ◽  
Vol 688 ◽  
Author(s):  
Tingkai Li ◽  
Sheng Teng Hsu ◽  
Bruce Ulrich ◽  
Lisa Stecker
Keyword(s):  
Gate Dielectric ◽  
Dielectric Material ◽  
Drain Current ◽  
Basic Mechanism ◽  
Memory Device ◽  
Ferroelectric Material ◽  
Channel Length ◽  
Ferroelectric Materials ◽  
Memory Devices ◽  
Transistor Fabrication

AbstractThe basic mechanism for one transistor memory device has been studied. Ferroelectric material, Pb5Ge3O11 (PGO) was selected for MFOS (M: Metal, F: Ferroelectrics, O: oxide, S: silicon) memory transistor fabrication. Processing of one-transistor memory devices dealt with the following issues: decomposition of ferroelectric materials, the etching damage of ferroelectric materials, the forming gas annealing damage of ferroelectric materials, the selective deposition of ferroelectric materials, the alignment for device making processes. The integration processes for one transistor memory device have been optimized to reduce process-induced damages. The gate dielectric material is (Zr, Hf)O2. Extremely high c-axis oriented Pb5Ge3O11 thin films were successfully deposited on high k gate oxide. Memory transistors having 0.6, 3 and 10μm channel length and 10 μm channel width have been fabricated. The memory windows are around 1 - 2V. The memory windows are almost saturated from operation voltage of 4V. After programming at -5V (on “off” state), the drain current (ID) at VD of 1V and VG of 2.5 V is about 1.15 ×10−10A. After programming at 5 V (on “on” state) the drain current (ID) at VD of 1V and VG of 2.5 V is measured about 6.4 ×10−8 A, which was 2.5 order higher than that of “off” state.

Effect of Varying Memory Device Architectures on the Electrical Properties of P(VDF/TrFE)(72/28) Copolymer Thin Film

2008 ◽  
Vol 54 ◽  
pp. 491-496 ◽  
Author(s):  
Chang Woo Choi ◽  
Arun Anand Prabu ◽  
Sun Yoon ◽  
Yu Min Kim ◽  
Kap Jin Kim
Keyword(s):  
Vinylidene Fluoride ◽  
Field Effect Transistors ◽  
Random Access ◽  
Drain Current ◽  
Random Copolymer ◽  
Memory Device ◽  
Channel Length ◽  
Memory Retention ◽  
Voltage Measurement ◽  
Electrical Measurements

In this study, the dipole switching and non-volatile memory functionality of poly(vinylidene fluoride-trifluoroethylene) (PVDF/TrFE)(72/28 mol%) random copolymer ultrathin films were analyzed. PVDF/TrFE(72/28) used as ferroelectric insulator in varying memory device architectures such as metal-ferroelectric polymer-metal (MFM), MF-insulator-semiconductor (MFIS), MIS and ferroelectric field-effect transistors (FeFET) were examined using different electrical measurements. A maximum data writing speed of 1.69 MHz was calculated from the switching time measured using MFM architecture. Compared to MFM, MFIS device architecture was found to be more suitable for distinguishing the ‘0’ and ‘1’ state using the capacitance-voltage measurement. With FeFET, the measured drain current (Id) as well as its memory window increased with decreasing channel length, thereby enabling the easier identification of ‘0’ and ‘1’ state comparable to the MFIS case. The data obtained from this study will be useful in the fabrication of non-volatile random access memory (NVRAM) devices operating at lower voltage with faster data R/W/E speed and memory retention capability.

Future Silicon Nanocrystal Nonvolatile Memory Technology

2001 ◽  
Vol 686 ◽  
Author(s):  
Michele L. Ostraat ◽  
Jan W. De Blauwe
Keyword(s):  
Threshold Voltage ◽  
Flash Memory ◽  
Nonvolatile Memory ◽  
Gate Dielectric ◽  
Oxide Thickness ◽  
Channel Length ◽  
Charge Storage ◽  
Memory Devices ◽  
Two Stage ◽  
Nanocrystal Memory

AbstractA great deal of research interest is being invested in the fabrication and characterization of nanocrystal structures as charge storage memory devices. In these flash memory devices, it is possible to measure threshold voltage shifts due to charge storage of only a few electrons per nanocrystal at room temperature. Although a variety of methods exist to fabricate nanocrystals and to incorporate them into device layers, control over the critical nanocrystal dimensions, tunnel oxide thickness, and interparticle separation and isolation remains difficult to achieve. This control is vital to produce reliable and consistent devices over large wafer areas. To address these control issues, we have developed a novel two-stage ultra clean reactor in which the Si nanocrystals are generated as single crystal, nonagglomerated, spherical aerosol particles from silane decomposition at 950°C at concentrations exceeding 108 cm−3 at sizes below 10 nm. Using existing aerosol instrumentation, it is possible to control the particle size to approximately 10% on diameter. In the second reactor, particles are passivated with a high quality oxide layer with shell thickness controllable from 0.7 to 2.0 nm. The two-stage aerosol reactor is integrated to a 200 mm wafer deposition chamber such that controlled particle densities can be deposited thermophoretically. With nanocrystal deposits of 1013 cm−2, contamination of transition metals and other elements can be controlled to less than 1010 atoms cm−2.We have fabricated 0.2 μm channel length aerosol nanocrystal floating gate memory devices using conventional MOS ULSI processing on 200 mm wafers. The aerosol nanocrystal memory devices exhibit normal transistor characteristics with drive current 30 μA/μm, subthreshold slope 200 mV/dec, and drain induced barrier lowering 100 mV/V, typical values for thick gate dielectric high substrate doped nonvolatile memory devices. Uniform Fowler-Nordheim tunneling is used to program and erase these memory devices. Despite 5 nm tunnel oxides, threshold voltage shifts > 2 V have been achieved with microsecond program and millisecond erase times at moderate operating voltages. The aerosol devices also exhibit excellent endurance cyclability with no window closure observed after 105 cycles. Furthermore, reasonable disturb times and long nonvolatility are obtained, illustrating the inherent advantage of discrete nanocrystal charge storage. No drain disturb was detected even at drain biases of 4V, indicating that little or no charge conduction occurs in the nanocrystal layer. We have demonstrated promise for aerosol nanocrystal memory devices. However, numerous issues exist for the future of nanocrystal devices. These technology issues and challenges will be discussed as directions for future work.

Fabrication and Electrical Studies of P(VDF/TrFE)(72/28) Copolymer based Non-Volatile Memory Devices as a Function of Varying Device Structures

2008 ◽  
Vol 1071 ◽  
Author(s):  
Kap Jin Kim ◽  
Chang Woo Choi ◽  
Arun Anand Prabu ◽  
Sun Yoon
Keyword(s):  
Random Access ◽  
Drain Current ◽  
Memory Device ◽  
Channel Length ◽  
Memory Retention ◽  
Electrical Measurements ◽  
Device Structure ◽  
Retention Capacity ◽  
Non Volatile Memory ◽  
Polymer Metal

AbstractFerroelectric characteristics of poly(vinylidiene fluoride/trifluoroethylene) (P(VDF/TrFE) (72/28 mol%)) copolymer ultrathin films used as an insulator in varying memory device architectures such as metal-ferroelectric polymer-metal (MFM), MF-insulator-semiconductor (MFIS), MIS and organic field-effect transistor (OFET) were studied using different electrical measurements. A maximum data writing speed of 1.69 MHz was calculated from the switching time measured using MFM architecture. Capacitance-voltage measured using MFIS was found to be more suitable for distinguishing the ‘0’ and ‘1’ state compared to MFM device structure. In OFET, the decreasing channel length increased the measured drain current (Id) values as well as its memory window enabling easier identification of the ‘0’ and ‘1’ state comparable to MFIS case. The data obtained from this study will be useful in the fabrication of non-volatile random access memory (NVRAM) devices with faster data R/W/E speed and memory retention capacity.

Materials Science Issues for the Fabrication of Nanocrystal Memory Devices by Ultra Low Energy Ion Implantation

2006 ◽  
Vol 258-260 ◽  
pp. 531-541 ◽  
Author(s):  
A. Claverie ◽  
Caroline Bonafos ◽  
G. Ben Assayag ◽  
S. Schamm ◽  
N. Cherkashin ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Materials Science ◽  
Gate Dielectric ◽  
Low Cost ◽  
Memory Device ◽  
Deep Submicron ◽  
Low Energy ◽  
Memory Devices ◽  
Mos Transistor ◽  
Nanocrystal Memory

Nanocrystal memories are attractive candidate for the development of non volatile memory devices for deep submicron technologies. In a nanocrystal memory device, a 2D network of isolated nanocrystals is buried in the gate dielectric of a MOS and replaces the classical polysilicon layer used in floating gate (flash) memories. Recently, we have demonstrated a route to fabricate these devices at low cost by using ultra low energy ion implantation. Obviously, all the electrical characteristics of the device depend on the characteristics of the nanocrystal population (sizes and densities) but also on their exact location with respect to the gate and channel of the MOS transistor. It is the goal of this paper to report on the main materials science aspects of the fabrication of 2D arrays of Si nanocrystals in thin SiO2 layers and at tunable distances from their SiO2/interfaces.

scholarly journals Simulations of the CNFETs using different high-k gate dielectrics

2020 ◽  
Vol 9 (3) ◽  
pp. 943-949
Author(s):  
Ankita Dixit ◽  
Navneet Gupta
Keyword(s):  
Carbon Nanotube ◽  
Field Effect ◽  
Gate Dielectric ◽  
Dielectric Material ◽  
Gate Dielectrics ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Dielectric Materials ◽  
High K ◽  
Gate Dielectric Material

In this paper we presented the analysis of Carbon Nanotube Field Effect Transistors (CNFETs) using various high-k gate dielectric materials. The objective of this work was to choose the best possible material for gate dielectric. This paper also presented the study on the effect of thickness of gate dielectric on the performance of the device. For the analysis (19, 0) CNT was considered because the diameter of (19, 0) CNT is 1.49nm and the CNFETs have been fabricated with the CNT diameter of ~1.5nm. It has been observed that La2O3 is the best gate dielectric material followed by HfO2 and ZrO2. It was also observed that as thickness of gate dielectric material reduces, drain current of CNFET increases. The outcomes of this study matches with the analytical results and hence confirm the results

Effect of Technology Scaling on MOS Transistor Performance with High-K Gate Dielectrics

2002 ◽  
Vol 716 ◽  
Author(s):  
Nihar R. Mohapatra ◽  
Madhav P. Desai ◽  
Siva G. Narendra ◽  
V. Ramgopal Rao
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Channel Length ◽  
Mos Transistors ◽  
Short Channel ◽  
Technology Scaling ◽  
Mos Transistor ◽  
Wide Range ◽  
Impact Of Technology ◽  
The Impact

AbstractThe impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations.

A self-assembling amphiphilic perylene bisimide and its application for WORM memory devices

2016 ◽  
Vol 40 (10) ◽  
pp. 8886-8891 ◽  
Author(s):  
Junfeng Li ◽  
Chenglong Yang ◽  
Ying Chen ◽  
Wen-Yong Lai
Keyword(s):  
Memory Device ◽  
Memory Devices ◽  
Perylene Bisimide ◽  
Self Assembling ◽  
External Stimuli

Morphologies of the amphiphilic perylene bisimide assemblies were controlled and switched by external stimuli to afford a good-performance WORM memory device.

Metal Oxide Thin Film Transistor with Nano Inorganic Gate Dielectric : Material Chemistry, Nanoscience, Solution Processing and Electronics

2021 ◽  
Vol 23 (09) ◽  
pp. 1078-1085
Author(s):  
A. Kanni Raj ◽  
Keyword(s):  
Thin Film ◽  
Metal Oxide ◽  
Gate Dielectric ◽  
Dielectric Material ◽  
Thin Film Transistor ◽  
Sol Gel ◽  
Oxide Thin Film ◽  
Barium Zirconate ◽  
Operating Voltage ◽  
Metal Oxide Thin Film

Indium Lead Oxide (ILO) based Metal Oxide Thin Film Transistor (MOTFT) is fabricated with Lead Barium Zirconate (PBZ) gate dielectric. PBZ is formed over doped silicon substrate by cheap sol-gel process. Thin film PBZ is analysed with X-ray Diffraction (XRD), Ultra-Violet Visible Spectra (UV-Vis) and Atomic Force Microscope (AFM). IZO is used as bottom gate to contact Thin Film Transistor (TFT). This device needs only 5V as operating voltage, and so is good for lower electronics <40V. It shows excellent emobility 4.5cm2/V/s, with on/off ratio 5×105 and sub-threshold swing 0.35V/decade.

Experimental and Theoretical Investigation of Minimization of Forming-Induced Variability in Resistive Memory Devices

2015 ◽  
Vol 1729 ◽  
pp. 53-58
Author(s):  
Brian L. Geist ◽  
Dmitri Strukov ◽  
Vladimir Kochergin
Keyword(s):  
Metal Oxide ◽  
Diffusion Processes ◽  
Memory Device ◽  
Device Fabrication ◽  
Oxide Material ◽  
Memory Devices ◽  
Resistive Memory ◽  
Conductive Filament ◽  
Metal Metal ◽  
Metal Oxide Layer

ABSTRACTResistive memory materials and devices (often called memristors) are an area of intense research, with metal/metal oxide/metal resistive elements a prominent example of such devices. Electroforming (the formation of a conductive filament in the metal oxide layer) represents one of the often necessary steps of resistive memory device fabrication that results in large and poorly controlled variability in device performance. In this contribution we present a numerical investigation of the electroforming process. In our model, drift and Ficks and Soret diffusion processes are responsible for movement of vacancies in the oxide material. Simulations predict filament formation and qualitatively agreed with a reduction of the forming voltage in structures with a top electrode. The forming and switching results of the study are compared with numerical simulations and show a possible pathway toward more repeatable and controllable resistive memory devices.

Flexible nonvolatile resistive memory devices based on SrTiO3 nanosheets and polyvinylpyrrolidone composites

2017 ◽  
Vol 5 (37) ◽  
pp. 9799-9805 ◽  
Author(s):  
Guilin Chen ◽  
Peng Zhang ◽  
Lulu Pan ◽  
Lin Qi ◽  
Fucheng Yu ◽  
...  
Keyword(s):  
Memory Effect ◽  
Resistive Switching ◽  
Memory Device ◽  
Memory Devices ◽  
Resistive Memory ◽  
Resistive Switching Memory ◽  
Switching Memory

A non-volatile resistive switching memory effect was observed in flexible memory device based on SrTiO3 nanosheets and polyvinylpyrrolidone composites.

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