Effect of Varying Memory Device Architectures on the Electrical Properties of P(VDF/TrFE)(72/28) Copolymer Thin Film

2008 ◽  
Vol 54 ◽  
pp. 491-496 ◽  
Author(s):  
Chang Woo Choi ◽  
Arun Anand Prabu ◽  
Sun Yoon ◽  
Yu Min Kim ◽  
Kap Jin Kim
Keyword(s):  
Vinylidene Fluoride ◽  
Field Effect Transistors ◽  
Random Access ◽  
Drain Current ◽  
Random Copolymer ◽  
Memory Device ◽  
Channel Length ◽  
Memory Retention ◽  
Voltage Measurement ◽  
Electrical Measurements

In this study, the dipole switching and non-volatile memory functionality of poly(vinylidene fluoride-trifluoroethylene) (PVDF/TrFE)(72/28 mol%) random copolymer ultrathin films were analyzed. PVDF/TrFE(72/28) used as ferroelectric insulator in varying memory device architectures such as metal-ferroelectric polymer-metal (MFM), MF-insulator-semiconductor (MFIS), MIS and ferroelectric field-effect transistors (FeFET) were examined using different electrical measurements. A maximum data writing speed of 1.69 MHz was calculated from the switching time measured using MFM architecture. Compared to MFM, MFIS device architecture was found to be more suitable for distinguishing the ‘0’ and ‘1’ state using the capacitance-voltage measurement. With FeFET, the measured drain current (Id) as well as its memory window increased with decreasing channel length, thereby enabling the easier identification of ‘0’ and ‘1’ state comparable to the MFIS case. The data obtained from this study will be useful in the fabrication of non-volatile random access memory (NVRAM) devices operating at lower voltage with faster data R/W/E speed and memory retention capability.

Fabrication and Electrical Studies of P(VDF/TrFE)(72/28) Copolymer based Non-Volatile Memory Devices as a Function of Varying Device Structures

2008 ◽  
Vol 1071 ◽  
Author(s):  
Kap Jin Kim ◽  
Chang Woo Choi ◽  
Arun Anand Prabu ◽  
Sun Yoon
Keyword(s):  
Random Access ◽  
Drain Current ◽  
Memory Device ◽  
Channel Length ◽  
Memory Retention ◽  
Electrical Measurements ◽  
Device Structure ◽  
Retention Capacity ◽  
Non Volatile Memory ◽  
Polymer Metal

AbstractFerroelectric characteristics of poly(vinylidiene fluoride/trifluoroethylene) (P(VDF/TrFE) (72/28 mol%)) copolymer ultrathin films used as an insulator in varying memory device architectures such as metal-ferroelectric polymer-metal (MFM), MF-insulator-semiconductor (MFIS), MIS and organic field-effect transistor (OFET) were studied using different electrical measurements. A maximum data writing speed of 1.69 MHz was calculated from the switching time measured using MFM architecture. Capacitance-voltage measured using MFIS was found to be more suitable for distinguishing the ‘0’ and ‘1’ state compared to MFM device structure. In OFET, the decreasing channel length increased the measured drain current (Id) values as well as its memory window enabling easier identification of the ‘0’ and ‘1’ state comparable to MFIS case. The data obtained from this study will be useful in the fabrication of non-volatile random access memory (NVRAM) devices with faster data R/W/E speed and memory retention capacity.

Improvement of Short Channel Mobility and Operational Stability of Pentacene Bottom-Contact Transistors with a Sulfuric Acid and Hydrogen Peroxide Mixture (SPM) Treatment of Au Electrodes

2006 ◽  
Vol 965 ◽  
Author(s):  
Haruo Kawakami ◽  
Takahiko Maeda ◽  
Hisato Kato
Keyword(s):  
Hydrogen Peroxide ◽  
Sulfuric Acid ◽  
Contact Resistance ◽  
Gate Voltage ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Channel Length ◽  
Short Channel ◽  
Bottom Contact

ABSTRACTWe report a reduction in the contact resistance between pentacene and Au source/drain electrodes of organic field effect transistors (OFETs) with bottom-contact structure. By immersing the Au electrodes in a sulfuric acid and hydrogen peroxide mixture (SPM), the injection barrier between the Au electrodes and pentacene was lowered by approximately 0.2 eV and the contact resistance significantly decreased. The fabricated bottom-contact OFETs revealed a field-effect mobility of more than 0.66 cm2/Vs at a channel length ranging from 3 to 30 μm, which is comparable to that of top-contact OFETs with a 50 μm channel length. The transfer characteristics of the OFET with the SPM treatment were stable even after 44days storage in air under room illumination without any passivation. Moreover, the drain current reduction due to threshold voltage (Vth) shift under continuous application of gate voltage quickly recovered toward the original value with unloading of gate voltage.

Ferroelectric 1-T memory device—will it be viable for nonvolatile memory applications?

2004 ◽  
Vol 830 ◽  
Author(s):  
Jin-Ping Han
Keyword(s):  
Buffer Layer ◽  
Retention Time ◽  
Nonvolatile Memory ◽  
High Speed ◽  
Random Access ◽  
Charge Trapping ◽  
Memory Device ◽  
Strong Impact ◽  
Memory Devices ◽  
Memory Retention

ABSTRACTThe quest for a nonvolatile memory FET based on the metal-ferroelectric-(insulator)-semiconductor (MF(I)S) gate stack concept has greatly intensified in recent years. In principle, such a memory device (MF(I)S) could be a building block of an ideal memory technology which offers random access, high speed, low power, high density and non-volatility. In practice, however, none of the reported ferroelectric memory transistors has achieved a memory retention time of more than a few days so far. These results are a far cry from the 10-year retention time requirement for non-volatile memory devices. This paper reveals progress and optimization that grain size, interfacial properties, and crystallinity of the annealed ferroelectric SrBi2Ta2O9 (SBT) films have a strong impact on the size of the memory window, as does the choice of the buffer layer material. The properties of SiN buffer layer sandwiched between SBT and Si are discussed. Switches in the polarization of the ferroelectric SBT play a key role for both the ferroelectric-polarization-dominated and the trapping-dominated memory windows. Preliminary results on MFIS capacitors and transistors are reviewed, limited retention time has been observed. A closer look at the physics of device operation reveals two major causes of the short retention time: (1) depolarization fields; (2) finite gate leakage current and the associated charge trapping. Here, the origins of these problems are analyzed and practical difficulties in attempting to realize nonvolatile ferroelectric 1-T memory devices are illustrated. Two possible solutions have been proposed to circumvent problems associated with the finite retention time in ferroelectric FETtype memories: (1) memory refreshes as done in the FEDRAM cell, (2) single-crystallize the ferroelectric film.

scholarly journals Revisiting Analytical Models of N-Type Symmetric Double-Gate MOSFETs Shaded Conditions

2020 ◽  
Vol 24 (1) ◽  
Author(s):  
Rekib Uddin Ahmed ◽  
Prabir Saha
Keyword(s):  
Integrated Circuits ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Cmos Technology ◽  
Channel Length ◽  
Oxide Semiconductor ◽  
Analytical Models ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects

Nowadays, the endlessly increasing demand for faster and complex integrated circuits (IC) has been fuelled by the scaling of metal-oxide-semiconductor field-effect-transistors (MOSFET) to smaller dimensions. The continued scaling of MOSFETs approaches its physical limits due to short-channel effects (SCE). Double-gate (DG) MOSFET is one of the promising alternatives as it offers better immunity towards SCEs and can be scaled to the shortest channel length. In future, ICs can be designed using DG-CMOS technology for which mathematical models depicting the electrical characteristics of the DG MOSFETs are foremost needed. In this paper, a review on n-type symmetric DG MOSFETs models has been presented based on the analyses of electrostatic potential distribution, threshold voltage, and drain-current models. Mathematical derivations of the device models are described elaborately, and numerical simulations are also carried out to validate the replicability of models.

Evaluation of the Vapor and Chemical Sensing Mechanism for Pentacene Field Effect Transistors

2010 ◽  
Vol 1253 ◽  
Author(s):  
Davianne A Duarte ◽  
Deepak Sharma ◽  
Brian Cobb ◽  
Ananth Dodabalapur
Keyword(s):  
Field Effect Transistors ◽  
High Mobility ◽  
Drain Current ◽  
Channel Length ◽  
Organic Thin Film ◽  
Lower Mobility ◽  
And Shifts ◽  
Increasing Temperature ◽  
Mobility Device ◽  
Alcohol Testing

AbstractProperties such as semicondutor film grain size, morphology, and channel length are known to effect the sensing response in pentacene based organic thin film transistors (OTFTs). The sensing behavior for low and high mobility pentacene devices are reported here exhibiting different temperature dependent behaviors. The lower mobility OTFT exhibits an expected thermally activated response during alcohol testing with an increasing mobility with temperature along with a decreasing mobility at each temperature for increasing concentration. The higher mobility device exhibits a decrease in mobility with increasing temperature along with a decrease in mobility with increasing concentration at each temperature. In both sets of devices, the polar analyte produced reductions in drain current and shifts in threshold voltage.

Integration Processes and Properties of Pt/Pb5Ge3O11/(Zr, Hf)O2/Si One Transistor Memory Devices

2001 ◽  
Vol 688 ◽  
Author(s):  
Tingkai Li ◽  
Sheng Teng Hsu ◽  
Bruce Ulrich ◽  
Lisa Stecker
Keyword(s):  
Gate Dielectric ◽  
Dielectric Material ◽  
Drain Current ◽  
Basic Mechanism ◽  
Memory Device ◽  
Ferroelectric Material ◽  
Channel Length ◽  
Ferroelectric Materials ◽  
Memory Devices ◽  
Transistor Fabrication

AbstractThe basic mechanism for one transistor memory device has been studied. Ferroelectric material, Pb5Ge3O11 (PGO) was selected for MFOS (M: Metal, F: Ferroelectrics, O: oxide, S: silicon) memory transistor fabrication. Processing of one-transistor memory devices dealt with the following issues: decomposition of ferroelectric materials, the etching damage of ferroelectric materials, the forming gas annealing damage of ferroelectric materials, the selective deposition of ferroelectric materials, the alignment for device making processes. The integration processes for one transistor memory device have been optimized to reduce process-induced damages. The gate dielectric material is (Zr, Hf)O2. Extremely high c-axis oriented Pb5Ge3O11 thin films were successfully deposited on high k gate oxide. Memory transistors having 0.6, 3 and 10μm channel length and 10 μm channel width have been fabricated. The memory windows are around 1 - 2V. The memory windows are almost saturated from operation voltage of 4V. After programming at -5V (on “off” state), the drain current (ID) at VD of 1V and VG of 2.5 V is about 1.15 ×10−10A. After programming at 5 V (on “on” state) the drain current (ID) at VD of 1V and VG of 2.5 V is measured about 6.4 ×10−8 A, which was 2.5 order higher than that of “off” state.

Sub-threshold-like charge transport in organic field effect transistor: A study on effective channel thickness

2015 ◽  
Vol 29 (28) ◽  
pp. 1550172
Author(s):  
A. K. Kavala ◽  
A. K. Mukherjee
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Thermionic Emission ◽  
Drain Current ◽  
Channel Length ◽  
Hole Injection ◽  
Emission Model ◽  
Short Channel ◽  
Channel Thickness ◽  
Effective Channel

A short channel organic field effect transistors (OFET) based on Pentacene, having channel length in the range of sub-micrometer, has been numerically modelled for low values of drain voltage. The output characteristics show a nonlinear concave increase of drain current for all values of gate voltages. This anomalous current-voltage behavior, which resembles sub-threshold characteristics of silicon FETs, shows a good match with earlier experimental reports on OFET at low drain voltages. The sub-threshold-like characteristics has been interpreted in light of thermionic-emission model because of the presence of hole injection barrier at drain (gold)/Pentacene interface. The associated analysis has facilitated to obtain a significant parameter, effective channel thickness [Formula: see text], for the first time in case of OFETs. It came out to be roughly 4 nm and 8 nm for experimental devices of poly(3-hexylthiophene-2,5-diyl) and Pentacene, respectively, while the numerically modelled device yielded a value of about 60 nm. Increase of [Formula: see text] with transverse gate electric field is also observed. Physical explanation of the observations is also presented.

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

scholarly journals Impact of device scaling on the electrical properties of MoS2 field-effect transistors

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Goutham Arutchelvan ◽  
Quentin Smets ◽  
Devin Verreck ◽  
Zubair Ahmed ◽  
Abhinav Gaur ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
Oxide Thickness ◽  
Channel Length ◽  
Contact Length ◽  
Power Performance ◽  
Semiconducting Materials ◽  
Large Area ◽  
Short Channel ◽  
Device Scaling ◽  
Performance Area

AbstractTwo-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices.

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