Dynamic Noise Margin Analysis of a Low Voltage Swing 8T SRAM Cell for Write Operation

2013 ◽  
pp. 136-140
Author(s):  
P. Upadhyay ◽  
R. Kar ◽  
D. Mandal ◽  
S. P. Ghoshal
Keyword(s):  
Low Voltage ◽  
Dynamic Noise ◽  
Noise Margin ◽  
Sram Cell ◽  
Voltage Swing ◽  
Margin Analysis

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

Power Efficient and Improved Noise Margin of Sram Cell for System on Chip Applications

2018 ◽  
Author(s):  
Sunil Kumar Ojha ◽  
O.P. Singh ◽  
G.R. Mishra ◽  
P.R. Vaya
Keyword(s):  
Major Part ◽  
System On Chip ◽  
Process Technology ◽  
Power Efficient ◽  
Technology Node ◽  
Noise Margin ◽  
Sram Cell ◽  
On Chip ◽  
Margin Analysis

Noise margin analysis of SRAM cell is became more crucial for on chip applications. Currently the technology is migrating towards less than 10nm node and hence it is necessary to measure the noise margin of SRAM cell very effectively, since memory is one of the major part of system on chips (SOCs) and Network on chips (NOCs) devices. If the margin is not calculated efficiently then it may leads to bad chip product and the whole device which contains this chip may not work as per the expectation. This further leads to low yield which increases the number of defective chips compared to good one. In this paper the noise margin analysis of SRAM cell is performed using 7nm process technology node using HSPICE simulator.

scholarly journals Reduced Voltage Scaling in Clock Distribution Networks

VLSI Design ◽  
2009 ◽  
Vol 2009 ◽  
pp. 1-7 ◽  
Author(s):  
Khader Mohammad ◽  
Ayman Dodin ◽  
Bao Liu ◽  
Sos Agaian
Keyword(s):  
Low Voltage ◽  
Distribution Networks ◽  
Power Reduction ◽  
Active Power ◽  
Minimum Area ◽  
Clock Distribution Networks ◽  
Noise Margin ◽  
Voltage Swing ◽  
Full Swing ◽  
Circuit Technique

We propose a novel circuit technique to generate a reduced voltage swing (RVS) signals for active power reduction on main buses and clocks. This is achieved without performance degradation, without extra power supply requirement, and with minimum area overhead. The technique stops the discharge path on the net that is swinging low at a certain voltage value. It reduces active power on the target net by as much as 33% compared to traditional full swing signaling. The logic 0 voltage value is programmable through control bits. If desired, the reduced-swing mode can also be disabled. The approach assumes that the logic 0 voltage value is always less than the threshold voltage of the nMOS receivers, which eliminate the need of the low to high voltage translation. The reduced noise margin and the increased leakage on the receiver transistors using this approach have been addressed through the selective usage of multithreshold voltage (MTV) devices and the programmability of the low voltage value.

scholarly journals SRAM CELL 6T AND 8T PARAMETRIC STABILITY ANALYSIS

2021 ◽  
Vol I (I) ◽  
Author(s):  
Bharathabau K
Keyword(s):  
Stability Analysis ◽  
High Speed ◽  
Memory Cell ◽  
Parametric Stability ◽  
Static Noise Margin ◽  
Noise Margin ◽  
Sram Cell ◽  
Margin Analysis ◽  
Static Noise ◽  
Technology Advances

As technology advances, the need for SRAM cells that may be utilised in high-speed applications grows. SRAM cells' static noise margin (SNM) is one of the most important variables to consider when designing a memory cell, and it is the main predictor of SRAM cell speed. The static noise margin will have an impact on the read and write margins. When it comes to the SRAM Cell's stability, the SNM is very important. For high-speed SRAMs, read/write margin analysis is critical since it affects how much data can be read and written. The simulation was run using Mentor Graphics' IC Station, which utilised 350nm technology rather than 180nm technology.

scholarly journals Estimation of Write Noise Margin for 6t SRAM Cell in CMOS 45nm technology.

2021 ◽  
Vol 23 (05) ◽  
pp. 211-215
Author(s):  
Hima Bindu Katikala ◽  
◽  
G. Ramana Murthy ◽  
P. Raja Rajeswari ◽  
P. Sai Charan ◽  
...  
Keyword(s):  
High Speed ◽  
Random Access ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Noise Margin ◽  
Sram Cell ◽  
Scaling Process ◽  
Memory Architectures ◽  
Margin Analysis ◽  
Static Noise

For high speed application the static random access memory is mostly demandable. Such kind of device should possess additive parameters that can withstand during transistor scaling process. Their exist static noise margin (SNM) which degrades the device performance of memory architectures, majorly observed at write and read operation create write noise margin (WNM) and read noise margin (RNM). In this paper we discuss about the basic design of 6 transistor SRAM (6T SRAM) using 180nm and 45nm CMOS technology in Cadence Virtuoso with write noise margin analysis. The propagation delay, power dissipation, WNM are measured for both the technologies and observed that WNM is relatively low in 45nm.

scholarly journals Starter for Voltage Boost Converter to Harvest Thermoelectric Energy for Body-Worn Sensors

Energies ◽  
2021 ◽  
Vol 14 (14) ◽  
pp. 4092
Author(s):  
Grzegorz Blakiewicz ◽  
Jacek Jakusz ◽  
Waldemar Jendernalik
Keyword(s):  
Threshold Voltage ◽  
Low Voltage ◽  
Boost Converter ◽  
Mos Transistors ◽  
Weak Inversion ◽  
Thermoelectric Energy ◽  
On Chip ◽  
Voltage Swing ◽  
High Output Voltage ◽  
High Output

This paper examines the suitability of selected configurations of ultra-low voltage (ULV) oscillators as starters for a voltage boost converter to harvest energy from a thermoelectric generator (TEG). Important properties of particularly promising configurations, suitable for on-chip implementation are compared. On this basis, an improved oscillator with a low startup voltage and a high output voltage swing is proposed. The applicability of n-channel native MOS transistors with negative or near-zero threshold voltage in ULV oscillators is analyzed. The results demonstrate that a near-zero threshold voltage transistor operating in the weak inversion region is most advantageous for the considered application. The obtained results were used as a reference for design of a boost converter starter intended for integration in 180-nm CMOS X-FAB technology. In the selected technology, the most suitable transistor available with a negative threshold voltage was used. Despite using a transistor with a negative threshold voltage, a low startup voltage of 29 mV, a power consumption of 70 µW, and power conversion efficiency of about 1.5% were achieved. A great advantage of the proposed starter is that it eliminates a multistage charge pump necessary to obtain a voltage of sufficient value to supply the boost converter control circuit.

Sign in / Sign up

Export Citation Format

Share Document