Drain-Engineered Reconfigurable Transistor Exhibiting Complementary Operation

In this paper, we propose and simulate a multifunctional transistor that exhibits device reconfigurability and realizes both nFET and pFET electrical characteristics when adequately biased. The use of this device will significantly reduce the transistor count in realizing sequential and combinational circuits and will result in highly compact design. The device uses a dual fin structure having a single mid-gap workfunction gate (∼4.65 eV) alongside dual metal (metal-silicide) drain regions. It employs n + / p + - i junctions at the source-channel interface along with the Schottky junctions at the channel-drain interface. In practice, metal-silicides such as erbium/ytterbium silicide (ErSi x /YbSi x ) for the n -drain and platinum silicide (PtSi) for the p -drain can be used as they provide smallest electron and hole Schottkybarrier heights (SBHs). Simulations carried out using calibrated parameters show better drive current (≈ 10 −2 −10 −3 A/ µ m) compared to the quantum tunneling current in simulated stateof-the-art multifunctional devices (≈ 10 −4 − 10 −5 A/ µ m). In addition, butterfly curves show symmetric high (NM H ) and low (NM L ) noise margins of 0.43V and 0.29V for zero and finite SBHs, respectively. The switching characteristics is shown to have an overshoot of ∼0.15 V for realistic SBHs which is then eliminated for the case of zero SBHs. In the last section, it is also demonstrated that a simplified structure having single mid-gap workfunction (∼4.65 eV) drain of Nickel silicide (NiSi) does not hamper the reconfigurability of the device. Index Terms —MOSFET, Multifunctional circuit, CMOS, Schottky junction.