scholarly journals ADVANCED ENCRYPTION STANDARD USING FPGA OVERNETWORK

2021 ◽  
pp. 32-39
Author(s):  
Hind Ali Abdul Hasan ◽  
Safaa Maijd Mohammed ◽  
Noor Hayder Abdul Ameer
Keyword(s):  
Advanced Encryption Standard ◽  
Brute Force ◽  
Mathematical Formula ◽  
System Form ◽  
Field Programmable ◽  
Time Required ◽  
The Way

The increase number of eavesdropping or cracker to attack the information and hack the privacy of people. So, the essential issue is making system capable of ciphering information with rapid speed. Due to the advance in computer eavesdropping and cracker that made them to analysis the way of ciphering in rapid speed way. The development in the computer especially in the rapid processer in the last decade create the breaching of any system is a matter of time. Owing to most of breaching ways are based on analysis of system that requireы to be breached and to try brute force on that system to crack it. However, the lacking of influential processers that are capable of breaching system since earlier processors are limit to number of instructions. It can be done in second, which was not sufficient trying to break the system using brute force. In addition, the time required is far away from getting valuable messages in the time that needed. So, the research gives the focus on performing rapid system for ciphering the information rapidly and changing the ciphering every few milliseconds. The changing of ciphering in every millisecond helps system form preventing the eavesdropping and cracker from imposing brute force on the system and hacking the messages and images. The system that created is based on Advanced Encryption Standard (AES), which is it very best performing algorithm in ciphering and deciphering since it doesn’t need complex mathematical formula. The research is about designing system that capable of performing AES by using high processer designed on Field programmable gate Area (FPGA). The ciphering of AES using FPGA helps minimize the time required to cipher the information. Also, the research will focus on ciphering and deciphering of images by AES using FPGA

Keamanan file dokumen menggunakan algoritme Advanced Encryption Standard pada aplikasi berbasis Android

JNANALOKA ◽  
2020 ◽  
pp. 11-23
Author(s):  
Emy Setyaningsih
Keyword(s):  
Advanced Encryption Standard ◽  
Brute Force ◽  
Statistical Attack

Seiring dengan peningkatan kemampuan perangkat mobile terutama media penyimpanan yang ukurannya semakin besar, memungkinkan pengguna menyimpan file dokumen penting ke perangkat mobile. File dokumen rahasia tersebut menjadi sangat rentan untuk diketahui, diam- bil atau bahkan dimanipulasi dan disalahgunakan oleh pihak lain yang tidak berhak mengakses perangkat mobile tersebut. Oleh karena itu, dibutuhkan aplikasi berbasis Android yang dapat melindungi file dokumen agar tidak dapat dibaca oleh orang lain. Salah satu metode yang dapat digunakan untuk melindungi file dokumen tersebut dari serangan pihak yang tidak bertanggung jawab adalah metode kriptografi. Algoritme kriptografi yang paling sering digunakan untuk mengamankan dokumen dalam bentuk teks adalah algoritme Advanced Encryption Standard (AES). Penelitian ini berhasil membangun aplikasi pengamanan file dokumen dengan format pe- nyimpanan *.pdf, *.doc, *.ppt dan *.xls menggunakan algoritme AES berbasis Android. Aplikasi yang dibangun memiliki kelebihan pada penggunaan kunci AES yang selalu berbeda untuk pro- ses enkripsi, sehingga lebih aman terhadap serangan brute-force. Penelitian ini juga melakukan perbandingan kinerja dari AES-128, AES-192 dan AES-256 berdasarkan kecepatan proses enkri- psi dan dekripsi. Berdasarkan pengujian yang dilakukan, kecepatan waktu enkripsi dan dekripsi tidak dipengaruhi oleh jenis format penyimpanan file, namun dipengaruhi oleh ukuran file dan ukuran kuncinya. Semakin besar ukuran file asli (plainteks) maka semakin besar pula kebutuhan waktu prosesnya. Proses enkripsi dan dekripsi menggunakan panjang kunci 128 bit juga membu- tuhkan waktu paling cepat dibandingkan menggunakan panjang kunci 256 bit. Hasil pengujian menggunakan uji analisis histogram, memperlihatkan histogram dari cipherteks relatif rata yang menunjukkan algoritme kriptografi AES aman terhadap statistical attack. Hasil ini menunjukkan bahwa aplikasi berbasis Android untuk keamanan dokumen menggunakan algoritme AES yang dibangun memiliki keamanan cukup tinggi serta cepat proses enkripsi dan dekripsinya.

High Speed FPGA Based 128-bit Advance Encryption Standard (AES)

2021 ◽  
Vol 11 ◽  
Author(s):  
Ibrahem M. T. Hamidi ◽  
Farah S. H. Al-aassi
Keyword(s):  
High Throughput ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Design Tool ◽  
Advanced Encryption Standard ◽  
Clock Frequency ◽  
Advance Encryption Standard ◽  
Field Programmable ◽  
Internal Component ◽  
Gate Array

Aim: Achieve high throughput 128 bits FPGA based Advanced Encryption Standard. Background: Field Programmable Gate Array (FPGA) provides an efficient platform for design AES cryptography system. It provides the capability to control over each bit using HDL programming language such as VHDL and Verilog which results an output speed in Gbps rang. Objective: Use Field Programmable Gate Array (FPGA) to design high throughput 128 bits FPGA based Advanced Encryption Standard. Method: Pipelining technique has used to achieve maximum possible speed. The level of pipelining includes round pipelining and internal component pipelining where number of registers inserted in particular places to increase the output speed. The proposed design uses combinatorial logic to implement the byte substitution. The s-box implemented using composed field arithmetic with 7 stages of pipelining to reduce the combinatorial logic level. The presented model has implemented using VHDL in Xilinix ISETM 14.4 design tool. Result: The achieved results were 18.55 Gbps at a clock frequency of 144.96 MHz and area of 1568 Slices in Spartan3 xc3s1000 hardware. Conclusion: The results show that the proposed design reaches a high throughput with acceptable area usage compare with other designs in the literature.

MyrrorBot : A Digital Assistant Based on Holistic User Models for Personalized Access to Online Services

2021 ◽  
Vol 39 (4) ◽  
pp. 1-34
Author(s):  
Cataldo Musto ◽  
Fedelucio Narducci ◽  
Marco Polignano ◽  
Marco De Gemmis ◽  
Pasquale Lops ◽  
...  
Keyword(s):  
Natural Language ◽  
Information Needs ◽  
Effective Interaction ◽  
Personal Digital Assistant ◽  
User Profiling ◽  
Online Services ◽  
Intent Recognition ◽  
User Models ◽  
Time Required ◽  
The Way

In this article, we present MyrrorBot , a personal digital assistant implementing a natural language interface that allows the users to: (i) access online services, such as music, video, news, and food recommendation s, in a personalized way, by exploiting a strategy for implicit user modeling called holistic user profiling ; (ii) query their own user models, to inspect the features encoded in their profiles and to increase their awareness of the personalization process. Basically, the system allows the users to formulate natural language requests related to their information needs. Such needs are roughly classified in two groups: quantified self-related needs (e.g., Did I sleep enough? Am I extrovert? ) and personalized access to online services (e.g., Play a song I like ). The intent recognition strategy implemented in the platform automatically identifies the intent expressed by the user and forwards the request to specific services and modules that generate an appropriate answer that fulfills the query. In the experimental evaluation, we evaluated both qualitative (users’ acceptance of the system, usability) as well as quantitative (time required to complete basic tasks, effectiveness of the personalization strategy) aspects of the system, and the results showed that MyrrorBot can improve the way people access online services and applications. This leads to a more effective interaction and paves the way for further development of our system.

scholarly journals On the Use of Magnetic RAMs in Field-Programmable Gate Arrays

2008 ◽  
Vol 2008 ◽  
pp. 1-9 ◽  
Author(s):  
Y. Guillemenet ◽  
L. Torres ◽  
G. Sassatelli ◽  
N. Bruchon
Keyword(s):  
Power Consumption ◽  
Random Access ◽  
Switching Scheme ◽  
Fpga Design ◽  
Gate Arrays ◽  
Magnetic Switching ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Time Required ◽  
Magnetic Tunneling

This paper describes the integration of field-induced magnetic switching (FIMS) and thermally assisted switching (TAS) magnetic random access memories in FPGA design. The nonvolatility of the latter is achieved through the use of magnetic tunneling junctions (MTJs) in the MRAM cell. A thermally assisted switching scheme helps to reduce power consumption during write operation in comparison to the writing scheme in the FIMS-MTJ device. Moreover, the nonvolatility of such a design based on either an FIMS or a TAS writing scheme should reduce both power consumption and configuration time required at each power up of the circuit in comparison to classical SRAM-based FPGAs. A real-time reconfigurable (RTR) micro-FPGA using FIMS-MRAM or TAS-MRAM allows dynamic reconfiguration mechanisms, while featuring simple design architecture.

scholarly journals Disease control as an optimization problem

PLoS ONE ◽  
2021 ◽  
Vol 16 (9) ◽  
pp. e0257958
Author(s):  
Miguel Navascués ◽  
Costantino Budroni ◽  
Yelena Guryanova
Keyword(s):  
Disease Control ◽  
Stochastic Models ◽  
Optimization Problem ◽  
Initial Conditions ◽  
Optimization Theory ◽  
Model Parameters ◽  
Grid Search ◽  
Brute Force ◽  
Time Required ◽  
Policy Optimization

In the context of epidemiology, policies for disease control are often devised through a mixture of intuition and brute-force, whereby the set of logically conceivable policies is narrowed down to a small family described by a few parameters, following which linearization or grid search is used to identify the optimal policy within the set. This scheme runs the risk of leaving out more complex (and perhaps counter-intuitive) policies for disease control that could tackle the disease more efficiently. In this article, we use techniques from convex optimization theory and machine learning to conduct optimizations over disease policies described by hundreds of parameters. In contrast to past approaches for policy optimization based on control theory, our framework can deal with arbitrary uncertainties on the initial conditions and model parameters controlling the spread of the disease, and stochastic models. In addition, our methods allow for optimization over policies which remain constant over weekly periods, specified by either continuous or discrete (e.g.: lockdown on/off) government measures. We illustrate our approach by minimizing the total time required to eradicate COVID-19 within the Susceptible-Exposed-Infected-Recovered (SEIR) model proposed by Kissler et al. (March, 2020).

scholarly journals Research on Intelligent Control System of Thermal Print Head Based on FPGA

2021 ◽  
Author(s):  
Yang Xu ◽  
Sheng Wang ◽  
Ying Peng
Keyword(s):  
Pid Control ◽  
Control Algorithm ◽  
Control Method ◽  
Print Quality ◽  
Fuzzy Pid ◽  
Single Chip ◽  
Fuzzy Pid Control ◽  
Print Head ◽  
Field Programmable ◽  
Time Required

Thermal print head heating realtime temperature fluctuations are too large, often causing damage to the print head heating point, resulting in poor print quality and unsatisfactory print results. Therefore, in order to improve the stability of the thermal print head during printing, and at the same time solve the inefficiency of the traditional single chip microcomputer control of the thermal print head heating method, a field programmable gate array (FPGA) based thermal print head heating control method is proposed. In order to control the core, the intelligent fuzzy PID control algorithm is used to ensure that the temperature of the print head can be stabilized quickly. Through simulation and experimental verification, it is shown that the intelligent fuzzy PID control algorithm greatly improves the temperature stabilization effect, and the time required to reach stability short, not only improve the printing accuracy, but also extend the life of the print head.

Smart Refrigerator with Recipe Assistance

2017 ◽  
Vol 8 (2) ◽  
pp. 51-61
Author(s):  
Aishwarya Gadgil ◽  
Vedija Jagtap ◽  
Pooja Kulkarni
Keyword(s):  
Internet Of Things ◽  
Smart Home ◽  
Rfid Tags ◽  
Creative Processes ◽  
Rfid Tag ◽  
Technological Revolution ◽  
Load Cells ◽  
Time Required ◽  
Intellectual Power ◽  
The Way

Internet of Things (IoT) will lead to a technological revolution that will change the way people live and interact with their surroundings. Intelligent appliances combined with multimedia capability have been emerging in everyone's life. Smart home is one of the prominent areas of intelligent advances. Kitchen is considered as the center of our house, where the refrigerator plays an important role. Smart Refrigerator with Recipe Assistance will help in automating the refrigerator. The authors propose a system that would track the stock of ingredients in the refrigerator with the help of RFID tags and load cells. According to the availability of ingredients a list of possible recipes is predicted and suggestions will be given to the user. Whenever an item is identified by a RFID tag, estimations on the usage of ingredients are made and we can get notifications about the scarce products. The system will also help in checking the availability of ingredients based on the recipe user wishes to cook. The time required by an individual for manually checking the availability of ingredients in the refrigerator and then thinking about what to cook is greatly reduced using this system. Most of the information is automatically generated using RFID tags. Once the user logins into the application he/ she will be suggested the possible list of recipes based on the availability. Human intellectual power then can be used for new creative processes rather than using it for routine chores.

scholarly journals An Empirical Investigation on System and Statement Level Parallelism Strategies for Accelerating Scatter Search Using Handel-C and Impulse-C

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-11
Author(s):  
M. Walton ◽  
O. Ahmed ◽  
G. Grewal ◽  
S. Areibi
Keyword(s):  
Optimization Problems ◽  
Scatter Search ◽  
Population Based ◽  
Field Programmable ◽  
Speed Up ◽  
Time Required ◽  
High Level ◽  
Level Parallelism ◽  
Code Optimizations ◽  
Established Population

Scatter Search is an effective and established population-based metaheuristic that has been used to solve a variety of hard optimization problems. However, the time required to find high-quality solutions can become prohibitive as problem sizes grow. In this paper, we present a hardware implementation of Scatter Search on a field-programmable gate array (FPGA). Our objective is to improve the run time of Scatter Search by exploiting the potentially massive performance benefits that are available through the native parallelism in hardware. When implementing Scatter Search we employ two different high-level languages (HLLs): Handel-C and Impulse-C. Our empirical results show that by effectively exploiting source-code optimizations, data parallelism, and pipelining, a 28x speed up over software can be achieved.

The Brute Force View

2021 ◽  
pp. 37-56
Author(s):  
Tamar Schapiro
Keyword(s):  
Theory Of Action ◽  
Brute Force ◽  
Intuitive Appeal ◽  
The Way

In this chapter, I consider a conception of inclination that haunts the theory of action. It is alluded to in metaphors, but it is almost never defended systematically. This “brute force view” holds that our relation to our inclinations is analogous to our relation to external, brute forces. The intuitive appeal of this view is that it seems to capture two features of the way our inclinations influence us: they exert asymmetric pressure on us, and they are non-voluntary. But it does not capture a third feature, namely the deliberative role inclinations play. I claim further that upon closer inspection, the brute force view does not, in fact, adequately capture the first two features. The reason is that the brute force view makes inclinations external to us, in the wrong way. It makes being inclined to φ‎ too unlike φ‎-ing.

A Fault Tolerant Parallelism Approach for Implementing High-Throughput Pipelined Advanced Encryption Standard

2016 ◽  
Vol 25 (09) ◽  
pp. 1650113 ◽  
Author(s):  
Hadi Mardani Kamali ◽  
Shaahin Hessabi
Keyword(s):  
High Throughput ◽  
Fault Tolerant ◽  
Single Point ◽  
Parallel Architecture ◽  
Point Of View ◽  
Advanced Encryption Standard ◽  
Main Loop ◽  
Pipelined Architecture ◽  
Field Programmable ◽  
Encryption Method

Advanced Encryption Standard (AES) is the most popular symmetric encryption method, which encrypts streams of data by using symmetric keys. The current preferable AES architectures employ effective methods to achieve two important goals: protection against power analysis attacks and high-throughput. Based on a different architectural point of view, we implement a particular parallel architecture for the latter goal, which is capable of implementing a more efficient pipelining in field-programmable gate array (FPGA). In this regard, all intermediate registers which have a role for unrolling the main loop will be removed. Also, instead of unrolling the main loop of AES algorithm, we implement pipelining structure by replicating nonpipelined AES architectures and using an auto-assigner mechanism for each AES block. By implementing the new pipelined architecture, we achieve two valuable advantages: (a) solving single point of failure problem when one of the replicated parts is faulty and (b) deploying the proposed design as a fault tolerant AES architecture. In addition, we put emphasis on area optimization for all four AES main functions to reduce the overhead associated with AES block replication. The simulation results show that the maximum frequency of our proposed AES architecture is 675.62[Formula: see text]MHz, and for AES128 the throughput is 86.5[Formula: see text]Gbps which is 30.9% better than its closest existing competitor.

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