scholarly journals Модель влияния смещения затвора при ионизирующем облучении МОП-структур

2020 ◽  
Vol 54 (2) ◽  
pp. 189
Author(s):  
О.В. Александров ◽  
С.А. Мокрушина
Keyword(s):  
Ionizing Radiation ◽  
Silicon Substrate ◽  
Gate Dielectric ◽  
Quantitative Model ◽  
Threshold Shift ◽  
Gate Bias ◽  
Surface Component ◽  
Mos Structures

The new quantitative model of influence of gate bias on the threshold shift of MOS-structures at the ionizing radiation which is based on the accounting of holes trapping in a thin border layer of gate dielectric on interface with a silicon substrate is developed. The model allows to describe the smooth growth of threshold shift with gate bias – approximately linear from a dose for a surface component and nonlinear for a volume component. The threshold shift at a negative gate bias is modelled on the basis of the accounting of holes generation at ionizing radiation in the border layer.

scholarly journals Модель термополевой нестабильности p-МОП-транзисторов при отрицательном смещении затвора

2020 ◽  
Vol 54 (2) ◽  
pp. 181
Author(s):  
О.В. Александров
Keyword(s):  
Silicon Substrate ◽  
Gate Dielectric ◽  
Inversion Layer ◽  
Surface States ◽  
Quantitative Model ◽  
Oxide Semiconductor ◽  
Mos Transistors ◽  
Ion Diffusion ◽  
Bias Temperature Instability ◽  
P Type

Abstract A new quantitative model of the negative-bias temperature instability (NBTI) of p -MOS (metal-oxide-semiconductor) transistors is developed. The model is based on the reaction of the depassivation of surface states at the Si–SiO_2 interphase boundary (IPB) and hydrogen-containing hole traps near the Si–SiO_2 IPB by positively charged hydrogen ions H^+, accumulated in the p ^+-type inversion layer of the silicon substrate. The dependences of the surface and space charges in p -MOS transistors on the NBTI time are controlled by the kinetics of H^+-ion diffusion and drift from the silicon substrate to the Si–SiO_2 IPB. The effect of the gate voltage on the NBTI is explained by the effect of the electric-field strength on the H^+ ion segregation coefficient at the Si–SiO_2 IPB. The relaxation of positive space charge introduced into the gate dielectric during NBTI is described by the tunnel discharge of oxide traps by silicon-substrate electrons.

Model of the Effect of the Gate Bias on MOS Structures under Ionizing Radiation

2020 ◽  
Vol 54 (2) ◽  
pp. 240-245
Author(s):  
O. V. Aleksandrov ◽  
S. A. Mokrushina
Keyword(s):  
Ionizing Radiation ◽  
Gate Bias ◽  
Mos Structures

Radiation Hardness for Silicon Oxide and Aluminum Oxide on 4H-SiC

2018 ◽  
Vol 924 ◽  
pp. 229-232 ◽  
Author(s):  
Anders Hallén ◽  
Sethu Saveda Suvanam
Keyword(s):  
Proton Irradiation ◽  
Silicon Oxide ◽  
Positive Charge ◽  
Gate Dielectric ◽  
Radiation Hardness ◽  
Flat Band ◽  
Capacitance Voltage ◽  
Cv Measurements ◽  
Radiation Hard ◽  
Mos Structures

The radiation hardness of two dielectrics, SiO2and Al2O3, deposited on low doped, n-type 4H-SiC epitaxial layers has been investigated by exposing MOS structures involving these materials to MeV proton irradiation. The samples are examined by capacitance voltage (CV) measurements and, from the flat band voltage shift, it is concluded that positive charge is induced in the exposed structures detectable for fluence above 1×1011cm-2. The positive charge increases with proton fluence, but the SiO2/4H-SiC structures are slightly more sensitive, showing that Al2O3can provide a more radiation hard passivation, or gate dielectric for 4H-SiC devices.

Light Emitting Diode with MOS Structures Containing Multiple-Stacked Si Quantum Dots

2007 ◽  
Vol 121-123 ◽  
pp. 557-560 ◽  
Author(s):  
J. Xu ◽  
Katsunori Makihara ◽  
Hidenori Deki ◽  
Yoshihiro Kawaguchi ◽  
Hideki Murakami ◽  
...  
Keyword(s):  
Quantum Dots ◽  
Luminescence Intensity ◽  
Room Temperature ◽  
Light Emission ◽  
Light Emitting Diode ◽  
Infrared Light ◽  
Gate Bias ◽  
Light Emitting ◽  
Mos Structures ◽  
Si Quantum Dots

Light emitting diode with MOS structures containing multiple-stacked Si quantum dots (QDs)/SiO2 was fabricated and the visible-infrared light emission was observed a room temperature when the negative gate bias exceeded the threshold voltage. The luminescence intensity was increased linearly with increasing the injected current density. The possible luminescence mechanism was briefly discussed and the delta P doping was performed to obtain the doped Si QDs and the improvement of EL intensity was demonstrated.

Research on Threshold Voltage Instability in SiC MOSFET Devices with Precision Measurement

2019 ◽  
Vol 954 ◽  
pp. 133-138
Author(s):  
Ao Liu ◽  
Song Bai ◽  
Run Hua Huang ◽  
Tong Tong Yang ◽  
Hao Liu
Keyword(s):  
Threshold Voltage ◽  
Precision Measurement ◽  
Gate Dielectric ◽  
Interface Traps ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Experimental Platform ◽  
Bias Stress ◽  
Voltage Instability ◽  
Voltage Drift

The mechanism of threshold voltage shift was studied. It is believed that the instability in threshold voltage during gate bias stress is due to capture of electrons by the SiC/gate dielectric interface traps and the gate dielectric near interface traps. New experimental platform was designed and built successfully. When positive stress or negative stress is applied to the gate, the change of threshold voltage occur immediately. After stress removal, the recovery of the threshold voltage occur soon. The change and recovery of threshold voltage are very sensitive to time. In order to get accurate threshold voltage drift data after high-temperature gate bias experiment, test of threshold voltage must be carried out immediately after the experiment.

The Dependence of Carrier Distribution on Gate Capacitance of α-IGZO TFTs

2014 ◽  
Vol 598 ◽  
pp. 361-364 ◽  
Author(s):  
Chih Chieh Hsu ◽  
Chien Hsun Wu
Keyword(s):  
Threshold Voltage ◽  
Computer Aided Design ◽  
Gate Dielectric ◽  
Oxide Thin Film ◽  
High Electron ◽  
Indium Gallium Zinc Oxide ◽  
Gate Bias ◽  
Carrier Distribution ◽  
Fully Depleted ◽  
Gate Capacitance

The capacitance-voltage (C–V) characteristics of inverted staggered amorphous indium–gallium–zinc-oxide thin film transistors (α-IGZO TFTs) with various dimensions are investigated by physics-based technology computer aided design (TCAD) simulation. For gate bias lower than the threshold voltage of the TFT, the electrons in the channel region are nearly fully depleted. It causes that the total gate capacitance is determined by the overlap region of gate, α-IGZO, and source/drain metals. When the applied gate bias is higher than the threshold voltage, the high electron density channel with density of ~6 × 1017 cm-3 and thickness of ~3-4 nm is observed near the interface of α-IGZO and gate dielectric. It results that the total gate capacitance is dominated by the gate to channel overlap. Quantitative analysis of the carrier distribution and energy band structures are utilized to study the physical mechanism underlying the C–V characteristics of the α-IGZO TFTs.

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