Section S1: Compact Modeling for Semiconductor Device, Sensor and IC Design

Beta-SiC is an ideal candidate material for use in semiconductor device applications. Currently, monocrystalline β-SiC thin films are epitaxially grown on {100} Si substrates by chemical vapor deposition (CVD). These films, however, contain a high density of defects such as stacking faults, microtwins, and antiphase boundaries (APBs) as a result of the 20% lattice mismatch across the growth interface and an 8% difference in thermal expansion coefficients between Si and SiC. An ideal substrate material for the growth of β-SiC is α-SiC. Unfortunately, high purity, bulk α-SiC single crystals are very difficult to grow. The major source of SiC suitable for use as a substrate material is the random growth of {0001} 6H α-SiC crystals in an Acheson furnace used to make SiC grit for abrasive applications. To prepare clean, atomically smooth surfaces, the substrates are oxidized at 1473 K in flowing 02 for 1.5 h which removes ∽50 nm of the as-grown surface. The natural {0001} surface can terminate as either a Si (0001) layer or as a C (0001) layer.

Download Full-text

Applications of SIMS to electronic materials and devices

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100133047 ◽

1992 ◽

Vol 50 (2) ◽

pp. 1682-1683

Author(s):

S.F. Corcoran

Keyword(s):

Depth Distribution ◽

Secondary Ion Mass Spectrometry ◽

Semiconductor Device ◽

Electronic Materials ◽

Profile Analysis ◽

Semiconductor Industry ◽

Small Diameter ◽

Depth Resolution ◽

Detection Sensitivity

Over the past decade secondary ion mass spectrometry (SIMS) has played an increasingly important role in the characterization of electronic materials and devices. The ability of SIMS to provide part per million detection sensitivity for most elements while maintaining excellent depth resolution has made this technique indispensable in the semiconductor industry. Today SIMS is used extensively in the characterization of dopant profiles, thin film analysis, and trace analysis in bulk materials. The SIMS technique also lends itself to 2-D and 3-D imaging via either the use of stigmatic ion optics or small diameter primary beams.By far the most common application of SIMS is the determination of the depth distribution of dopants (B, As, P) intentionally introduced into semiconductor materials via ion implantation or epitaxial growth. Such measurements are critical since the dopant concentration and depth distribution can seriously affect the performance of a semiconductor device. In a typical depth profile analysis, keV ion sputtering is used to remove successive layers the sample.

Download Full-text

Structural and electronic properties of defects in semiconductors

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100136398 ◽

1995 ◽

Vol 53 ◽

pp. 4-5

Author(s):

J.L. Batstone

Keyword(s):

Semiconductor Device ◽

Chemical Vapor ◽

Misfit Strain ◽

Organic Chemical ◽

Extended Defects ◽

Transmission Electron ◽

Semiconductor Thin Films ◽

Wide Range ◽

Metal Organic ◽

Film Substrate

The development of growth techniques such as metal organic chemical vapor deposition (MOCVD) and molecular beam epitaxy during the last fifteen years has resulted in the growth of high quality epitaxial semiconductor thin films for the semiconductor device industry. The III-V and II-VI semiconductors exhibit a wide range of fundamental band gap energies, enabling the fabrication of sophisticated optoelectronic devices such as lasers and electroluminescent displays. However, the radiative efficiency of such devices is strongly affected by the presence of optically and electrically active defects within the epitaxial layer; thus an understanding of factors influencing the defect densities is required.Extended defects such as dislocations, twins, stacking faults and grain boundaries can occur during epitaxial growth to relieve the misfit strain that builds up. Such defects can nucleate either at surfaces or thin film/substrate interfaces and the growth and nucleation events can be determined by in situ transmission electron microscopy (TEM).

Download Full-text

Metal Microstructures in Advanced CMOS Devices

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100164258 ◽

1996 ◽

Vol 54 ◽

pp. 358-359

Author(s):

L. M. Gignac ◽

K. P. Rodbell

Keyword(s):

Grain Boundaries ◽

Semiconductor Device ◽

Chemical Vapor ◽

Microstructural Characterization ◽

Metal Films ◽

Thin Metal ◽

Electrical Performance ◽

Thin Metal Films ◽

Chemical Vapor Deposited ◽

Boundary Properties

As advanced semiconductor device features shrink, grain boundaries and interfaces become increasingly more important to the properties of thin metal films. With film thicknesses decreasing to the range of 10 nm and the corresponding features also decreasing to sub-micrometer sizes, interface and grain boundary properties become dominant. In this regime the details of the surfaces and grain boundaries dictate the interactions between film layers and the subsequent electrical properties. Therefore it is necessary to accurately characterize these materials on the proper length scale in order to first understand and then to improve the device effectiveness. In this talk we will examine the importance of microstructural characterization of thin metal films used in semiconductor devices and show how microstructure can influence the electrical performance. Specifically, we will review Co and Ti silicides for silicon contact and gate conductor applications, Ti/TiN liner films used for adhesion and diffusion barriers in chemical vapor deposited (CVD) tungsten vertical wiring (vias) and Ti/AlCu/Ti-TiN films used as planar interconnect metal lines.

Download Full-text

Behavior of contact-silicided TFSOI gate structures

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100172036 ◽

1994 ◽

Vol 52 ◽

pp. 860-861

Author(s):

N. David Theodore ◽

Juergen Foerstner ◽

Peter Fejes

Keyword(s):

Semiconductor Device ◽

Series Resistance ◽

Field Effect Transistors ◽

Silicon Layer ◽

Device Fabrication ◽

Silicon On Insulator ◽

Continuous Layer ◽

Buried Oxide ◽

Device Structures ◽

Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

Download Full-text

Digitally-Assisted Analog and Analog-Assisted Digital IC Design

10.1017/cbo9781316156148 ◽

2015 ◽

Cited By ~ 4

Keyword(s):

Ic Design

Download Full-text

Analogue IC Design: The Current-Mode Approach

10.1049/pbcs002e ◽

1993 ◽

Cited By ~ 113

Keyword(s):

Current Mode ◽

Ic Design

Download Full-text