The impact of very high speed integrated circuit technology on SpaceStation logistics

1988 ◽  
Author(s):  
LINCOLN HALLEN
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
The Impact ◽  
Circuit Technology ◽  
Very High

scholarly journals SYNTHESIS AND FPGA–IMPLEMENTATION BASED NEURAL TECHNIQUE OF A NONLINEAR ADC MODEL

2014 ◽  
pp. 27-33
Author(s):  
Mounir Bouhedda ◽  
Mokhtar Attari
Keyword(s):  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Description Language ◽  
Description Language ◽  
Analog To Digital ◽  
Field Programmable ◽  
Hardware Description ◽  
Nonlinear Analog ◽  
Very High

The aim of this paper is to introduce a new architecture using Artificial Neural Networks (ANN) in designing a 6-bit nonlinear Analog to Digital Converter (ADC). A study was conducted to synthesise an optimal ANN in view to FPGA (Field Programmable Gate Array) implementation using Very High-speed Integrated Circuit Hardware Description Language (VHDL). Simulation and tests results are carried out to show the efficiency of the designed ANN.

scholarly journals Sources of the Measurement Error of the Impact Pressure in Sloshing Experiments

2019 ◽  
Vol 7 (7) ◽  
pp. 207
Author(s):  
Dong Hwi Kim ◽  
Eun Soo Kim ◽  
Sung-chul Shin ◽  
Sun Hong Kwon
Keyword(s):  
Integrated Circuit ◽  
Measurement Errors ◽  
High Speed ◽  
Pressure Sensors ◽  
Pressure Measurements ◽  
Sensor Surface ◽  
Experimental Conditions ◽  
Surface Conditions ◽  
Peak Pressures ◽  
The Impact

Sloshing experiments have increasingly received academic attention. Understanding the measurement errors in the sloshing impact pressures is an important parts of the sloshing experiments since these errors, which arise from experimental conditions, affect the subsequent results. As part of the research on the sources of the measurement errors, focused on the effects of surface conditions of pressure sensors on the measurement of impact pressures. Thirty-six integrated circuit piezoelectric pressure sensors were placed on the upper surfaces of a two-dimensional tank to measure the sloshing impact pressures under surge or pitch motions. For each motion, the experimental conditions were divided in two based on whether the surfaces of the sensors were dry or wet. The peak pressures of each test were measured as twenty repeated experiments to ensure reliability. The flow in the tank was visualized using a high-speed camera to observe and analyze macroscopic and microscopic phenomena along the sensor surface. Thermal shock effects were confirmed by varying the experimental temperature and that of the sensor surface. The effects of the wet surface and droplets formed on the sensor surface on pressure measurements are discussed.

scholarly journals Study on the Impact of Lead Sidewall Solder Coverage and Corner Lead Size on Joint Reliability

2021 ◽  
pp. 62-69
Author(s):  
Jefferson Talledo
Keyword(s):  
Solder Joint ◽  
Integrated Circuit ◽  
High Speed ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Element Analysis ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Solder Fatigue ◽  
The Impact

Solder joint reliability is very important to ensure that an integrated circuit (IC) semiconductor package is functional within its intended life span as the solder joint establishes electrical connection between the IC and the printed circuit board (PCB). Solder fatigue failure or crack under thermal cycling is one of the common problems with board-mounted packages. There are several factors or package characteristics that have impact on solder fatigue life like package size and material properties of the package components. This paper presents a thermo-mechanical modeling of a leadframe-based semiconductor package to study the impact of lead sidewall solder coverage and corner lead size on the solder joint reliability. Finite element analysis (FEA) technique was used to calculate the solder life considering 50% and 100% package lead sidewall solder coverage as well as smaller and larger critical corner leads of the package. The results of the analysis showed that higher lead sidewall solder coverage and larger lead could significantly increase solder life. Therefore, ensuring lead sidewall solder wettability to have higher solder coverage is beneficial. The study also reveals that packages with side wettable flanks are not only enabling high speed automated optical inspection required for the automotive industry, but they are also providing improved solder joint reliability.

scholarly journals Meander-DGS Effect on Electromagnetic Bandgap Structure for Power/Ground Noise Suppression in High-Speed Integrated Circuit Packages and PCBs

Electronics ◽  
2022 ◽  
Vol 11 (2) ◽  
pp. 211
Author(s):  
Myunghoi Kim
Keyword(s):  
Slow Wave ◽  
Integrated Circuit ◽  
Analytical Method ◽  
High Speed ◽  
Noise Suppression ◽  
Cutoff Frequency ◽  
Closed Form Expression ◽  
Electromagnetic Bandgap ◽  
Ground Noise ◽  
The Impact

In this paper, we present the impact of a meander-shaped defected ground structure (MDGS) on the slow-wave characteristics of a lowest-order passband and a low cutoff frequency of the first stopband of an electromagnetic bandgap (EBG) structure for power/ground noise suppression in high-speed integrated circuit packages and printed circuit boards (PCBs). A semi-analytical method is presented to rigorously analyze the MDGS effect. In the analytical method, a closed-form expression for a low cutoff frequency of the MDGS-EBG structure is extracted with an effective characteristic impedance and a slow-wave factor. The proposed analytical method enables the fast analysis of the MDGS-EBG structure so that it can be easily optimized. The analysis of the MDGS effect revealed that the low cutoff frequency increases up to approximately 19% while comparing weakly and strongly coupled MDGSs. It showed that the miniaturization of the MDGS-EBG structure can be achieved. It was experimentally verified that the low cutoff frequency is reduced from 2.54 GHz to 2.00 GHz by decreasing the MDGS coupling coefficient, which is associated with the miniaturization of the MDGS-EBG structure in high-speed packages and PCBs.

scholarly journals Evaluation of the Potential Electromagnetic Interference in Vertically Stacked 3D Integrated Circuits

2020 ◽  
Vol 10 (3) ◽  
pp. 748
Author(s):  
Dipesh Kapoor ◽  
Cher Ming Tan ◽  
Vivek Sangwan
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Electromagnetic Interference ◽  
High Speed ◽  
High Performance ◽  
Near Field ◽  
Three Dimensional ◽  
3D Ic ◽  
Three Dimensional Integrated Circuit ◽  
The Impact

Advancements in the functionalities and operating frequencies of integrated circuits (IC) have led to the necessity of measuring their electromagnetic Interference (EMI). Three-dimensional integrated circuit (3D-IC) represents the current advancements for multi-functionalities, high speed, high performance, and low-power IC technology. While the thermal challenges of 3D-IC have been studied extensively, the influence of EMI among the stacked dies has not been investigated. With the decreasing spacing between the stacked dies, this EMI can become more severe. This work demonstrates the potential of EMI within a 3D-IC numerically, and determines the minimum distance between stack dies to reduce the impact of EMI from one another before they are fabricated. The limitations of using near field measurement for the EMI study in stacked dies 3D-IC are also illustrated.

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