scholarly journals Evaluation of the Potential Electromagnetic Interference in Vertically Stacked 3D Integrated Circuits

2020 ◽  
Vol 10 (3) ◽  
pp. 748
Author(s):  
Dipesh Kapoor ◽  
Cher Ming Tan ◽  
Vivek Sangwan
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Electromagnetic Interference ◽  
High Speed ◽  
High Performance ◽  
Near Field ◽  
Three Dimensional ◽  
3D Ic ◽  
Three Dimensional Integrated Circuit ◽  
The Impact

Advancements in the functionalities and operating frequencies of integrated circuits (IC) have led to the necessity of measuring their electromagnetic Interference (EMI). Three-dimensional integrated circuit (3D-IC) represents the current advancements for multi-functionalities, high speed, high performance, and low-power IC technology. While the thermal challenges of 3D-IC have been studied extensively, the influence of EMI among the stacked dies has not been investigated. With the decreasing spacing between the stacked dies, this EMI can become more severe. This work demonstrates the potential of EMI within a 3D-IC numerically, and determines the minimum distance between stack dies to reduce the impact of EMI from one another before they are fabricated. The limitations of using near field measurement for the EMI study in stacked dies 3D-IC are also illustrated.

Analyzing the Impact of X-Ray Tomography on the Reliability of Integrated Circuits

2015 ◽  
Author(s):  
Halit Dogan ◽  
Md Mahbub Alam ◽  
Navid Asadizanjani ◽  
Sina Shahbazmohamadi ◽  
Domenic Forte ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
3D Imaging ◽  
Three Dimensional ◽  
Serial Sectioning ◽  
Promising Technique ◽  
Flash Memories ◽  
X Ray ◽  
3D Information ◽  
The Impact

Abstract X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major finding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

Pre-Applied Inter Chip Fill for 3D-IC Chip Joining

2015 ◽  
Author(s):  
Yasuhiro Kawase ◽  
Makoto Ikemoto ◽  
Masaya Sugiyama ◽  
Hidehiro Yamamoto ◽  
Hideki Kiritani
Keyword(s):  
Thermal Conductivity ◽  
Integrated Circuits ◽  
High Performance ◽  
Three Dimensional ◽  
Conductive Filler ◽  
3D Ic ◽  
Fine Pitch ◽  
Silica Filler ◽  
Conductive Fillers ◽  
Process Compatibility

Three dimensional integrated circuits (3D-IC) have been proposed for the purpose of low power and high performance in recent years. Pre-applied inter chip fill is required for fine pitch interconnections, large chips, and also thin chips. In addition to them, pre-applied joining process with high thermal conductive inter chip fill (HT-ICF) is strongly required for the cooling of 3D-IC. Some kinds of matrix resins and thermal conductive fillers were simulated and evaluated for pre-applied ICF. As a result, matrix and cure agent appeared to be important to both pre-applied ICF process compatibility and thermal conductivity, so that we’d selected epoxy type matrix based on controlling super molecular structure due to its mesogen unit. And not only matrix but also filler appeared to be the key to improve thermal conductivity for pre-applied ICF at the same time. The thermal conductivity of conventional silica filler was only 1W/mK, so that, taking into account of thermal conductivity, density and its stability, we’d selected aluminum oxide and boron nitride as thermal conductive filler and optimized HT-ICF for pre-applied process. After composite was mixed and cured, some physical properties were measured and thermal conductivity was 1.8W/mK, CTE was below 21ppm/K and Tg was 120°C. Furthermore, new high thermal conductive filler was also studied. We’d synthesized completely new spherical BN (diameter <5um) and applied it to HT-ICF and the thermal conductivity was almost two times higher than conventional BN. In this study, we confirmed ICF physical characteristics and its pre-applied joining for 3D-IC and void-less joining was also discussed.

Layout Based Full Chip Thermal Simulations of Stacked 3D Integrated Circuits

2003 ◽  
Author(s):  
Ashok Raman ◽  
Marek Turowski ◽  
Monte Mar
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Hot Spots ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
3D Ic ◽  
Localized Heating ◽  
3D Integrated Circuits ◽  
Thermal Simulations

This paper presents full-chip scale detailed thermal simulations of three-dimensional (3D) integrated circuit (IC) stacks. The inter-layer dielectric (ILD) and inter-metal dielectric (IMD) materials inside 3D IC stacks may cause extensive localized heating. The influence of multiple layers of dielectrics on heat trapping inside the 3D stack is analyzed. Different methods to minimize such localized heating are studied. It is shown that the use of thermal vias is very effective in heat dissipation from the hot spots. Comparisons are made between several 3D IC configurations to verify these conclusions.

Low Temperature Cu–Cu Bonding Technology in Three-Dimensional Integration: An Extensive Review

2018 ◽  
Vol 140 (1) ◽  
Author(s):  
Asisa Kumar Panigrahy ◽  
Kuan-Neng Chen
Keyword(s):  
Low Temperature ◽  
Integrated Circuit ◽  
Large Scale ◽  
Three Dimensional ◽  
3D Ic ◽  
Bonding Technology ◽  
Three Dimensional Integrated Circuit ◽  
Low Temperature Bonding ◽  
Cu Bonding

Arguably, the integrated circuit (IC) industry has received robust scientific and technological attention due to the ultra-small and extremely fast transistors since past four decades that consents to Moore's law. The introduction of new interconnect materials as well as innovative architectures has aided for large-scale miniaturization of devices, but their contributions were limited. Thus, the focus has shifted toward the development of new integration approaches that reduce the interconnect delays which has been achieved successfully by three-dimensional integrated circuit (3D IC). At this juncture, semiconductor industries utilize Cu–Cu bonding as a key technique for 3D IC integration. This review paper focuses on the key role of low temperature Cu–Cu bonding, renaissance of the low temperature bonding, and current research trends to achieve low temperature Cu–Cu bonding for 3D IC and heterogeneous integration applications.

Fabrication of 3D-IC Interposers

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001295-001321
Author(s):  
John T. Keech ◽  
Garret Piech ◽  
Scott Pollard
Keyword(s):  
Integrated Circuit ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
Cost Savings ◽  
Cost Effective ◽  
Quality Parameters ◽  
Substrate Material ◽  
3D Ic ◽  
And Performance ◽  
Three Dimensional Integrated Circuit

Interposer fabrication has gained a lot of attention in the area of three-dimensional integrated circuit (3D-IC) integration. Glass has many properties that make it well suited for interposer substrates, such as adjustable coefficient of thermal expansion, advantaged electrical properties and unique forming processes. Furthermore, glass based solutions can also provide significant cost advantages in substrate material, via formation, and subsequent processing. In this paper, we will cover how fusion formed glass provides cost-effective solutions for the manufacturing of interposer substrates. Leveraging the ability to create through-glass-via (TGV) substrates in as-formed 100 μm thick precision glass, with a pristine surface, can avoid the need for back grinding and polishing operations. This has the potential to eliminate several manufacturing steps for polishing and thinning, while providing associated cost savings. Significant progress has been made in demonstration of TGV technology. Fully populated wafers with 100,000s of through or blind holes (≥ 25 μm diameter) are fabricated today, and 10–20 μm diameters are in development. We will report on important quality parameters measured on TGV wafers and positive implications with respect to product quality and strength. The ability to leverage industry metallization techniques and performance characteristics will also be reported. Finally, we will discuss opportunities to leverage cost-effective glass interposer solutions.

Overview and Outlook of Three-Dimensional Integrated Circuit Packaging, Three-Dimensional Si Integration, and Three-Dimensional Integrated Circuit Integration

2014 ◽  
Vol 136 (4) ◽  
Author(s):  
John H. Lau
Keyword(s):  
Integrated Circuit ◽  
State Of The Art ◽  
Three Dimensional ◽  
High Volume ◽  
3D Integration ◽  
3D Ic ◽  
3D Ic Packaging ◽  
Ic Packaging ◽  
Circuit Integration ◽  
Three Dimensional Integrated Circuit

3D integration consists of 3D integrated circuit (IC) packaging, 3D Si integration, and 3D IC integration. They are different and in general the through-silicon via (TSV) separates 3D IC packaging from 3D Si/IC integrations since the latter two use TSV but 3D IC packaging does not. 3D Si integration and 3D IC integration are different. 3D IC integration stacks up the thin chips with TSV and microbump, while 3D Si integration stacks up thin wafers with TSV alone (i.e., bumpless). TSV is the heart of 3D Si/IC integrations and is the focus of this investigation. Also, the state-of-the-art, challenge, and trend of 3D integration will be presented and examined. Furthermore, supply chain readiness for high volume manufacturing (HVM) of TSVs is discussed.

scholarly journals Fast 3D Integrated Circuit Placement Methodology using Merging Technique

2019 ◽  
Vol 69 (3) ◽  
pp. 217-222 ◽  
Author(s):  
Srinivas Sabbavarapu ◽  
Amit Acharyya ◽  
P. Balasubramanian ◽  
C. Ramesh Reddy
Keyword(s):  
Form Factor ◽  
Low Power ◽  
Integrated Circuit ◽  
High Speed ◽  
High Performance ◽  
Three Dimensional ◽  
Heterogeneous Systems ◽  
Reduced Form ◽  
Wire Length ◽  
Ic Design

In the recent years the advancement in the field of microelectronics integrated circuit (IC) design technologies proved to be a boon for design and development of various advanced systems in-terms of its reduction in form factor, low power, high speed and with increased capacity to incorporate more designs. These systems provide phenomenal advantage for armoured fighting vehicle (AFV) design to develop miniaturised low power, high performance sub-systems. One such emerging high-end technology to be used to develop systems with high capabilities for AFVs is discussed in this paper. Three dimensional IC design is one of the emerging field used to develop high density heterogeneous systems in a reduced form factor. A novel grouping based partitioning and merge based placement (GPMP) methodology for 3D ICs to reduce through silicon vias (TSVs) count and placement time is proposed. Unlike state-of-the-art techniques, the proposed methodology does not suffer from initial overlap of cells during intra-layer placement which reduces the placement time. Connectivity based grouping and partitioning ensures less number of TSVs and merge based placement further reduces intra layer wire-length. The proposed GPMP methodology has been extensively against the IBMPLACE database and performance has been compared with the latest techniques resulting in 12 per cent improvement in wire-length, 13 per cent reduction in TSV and 1.1x improvement in placement time.

A Micro-channel Cooling Model For a Three-dimensional Integrated Circuit Considering Through-silicon Vias

2020 ◽  
Vol 12 ◽  
Author(s):  
Kang-Jia Wang ◽  
Hong-Chang Sun ◽  
Kui-Zhi Wang
Keyword(s):  
Integrated Circuit ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
Micro Channel ◽  
3D Ic ◽  
Through Silicon Vias ◽  
3D Ics ◽  
Three Dimensional Integrated Circuit ◽  
Silicon Vias ◽  
Cooling Model

Background: With the increase of the integration degree of the three-dimensional integrated circuit(3D IC), the thermal power consumption per unit volume increases greatly, which makes the chip temperature rise. High temperature could affect the performance of the devices and even lead to thermal failure. So, the thermal management for 3D ICs is becoming a major concern. Objective: The aim of the research is to establish a micro-channel cooling model for a three-dimensional integrated circuit(3D IC) considering the through-silicon vias(TSVs). Methods: By studying the structure of the TSVs, the equivalent thermal resistance of each layer is formulated. Then the one-dimensional micro-channel cooling thermal analytical model considering the TSVs was proposed and solved by the existing sparse solvers such as KLU. Results: The results obtained in this paper reveal that the TSVs can effectively improve the heat dissipation, and its maximal temperature reduction is about 10.75%. The theoretical analysis is helpful to optimize the micro-channel cooling system for 3D ICs. Conclusion: The TSV has an important influence on the heat dissipation of 3D IC, which can improve its heat dissipation characteristic

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