scholarly journals METHOD OF IONIC MIXING FOR SILICIDE LAYER FORMATION

2020 ◽  
pp. 868-874
Author(s):  
Гасан Абакарович Мустафаев ◽  
Арслан Гасанович Мустафаев ◽  
Валерий Александрович Панченко ◽  
Наталья Васильевна Черкесова
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Ohmic Contacts ◽  
Limiting Factors ◽  
Silicide Formation ◽  
Layer Formation ◽  
Surface Layers ◽  
Silicide Layer ◽  
Parasitic Resistance ◽  
Metal Silicides

Ионная имплантация ионами отдачи или ионное перемешивание, основанное на внедрении требуемой примеси из поверхностных слоев при передаче им кинетической энергии первичного пучка, имеют большие перспективы для получения структур и соединений с заданными свойствами. В процессе масштабирования сверхбольших интегральных схем паразитное сопротивление межсодинений и неомический характер контактов являются ограничивающими факторами. Перспективными материалами для использования в системах металлизации являются силициды тугоплавких металлов. В работе проведено исследование по внедрению ионов фосфора в систему молибден-кремний. Полученные результаты демонстрируют возможность формирования силицида молибдена при пониженной температуре, применением имплантации ионов, вызывающих ионное перемешивание. Разработанная технология позволяет достичь однородной границы раздела силицида с кремнием, и необходимые электрофизические характеристики метализации и омических контактов. Из-за заглубления границы раздела в объем полупроводника снижается влияние состояния поверхности кремния на параметры омических контактов, в результате обеспечивается их необходимая стабильность и воспроизводимость. Ion implantation with recoil ions or ion mixing based on the introduction of the required impurity from the surface layers during the transfer of the kinetic energy of the primary beam to them have great prospects for obtaining structures and compounds with desired properties. In the process of ranging of very large scale integrated circuits, the parasitic resistance of interconnections and the nonohmic nature of contacts are the limiting factors. Refractory metal silicides are promising materials for use in metallization systems. In this work a study was carried out on the introduction of phosphorus ions into molybdenum-silicon systems. The results obtained demonstrate the possibility of the molybdenum silicide formation at a low temperature using implantation of ions that cause ionic mixing. The developed technology makes it possible to achieve a homogeneous interface between the silicide and silicon with the necessary electrophysical characteristics of metalization and ohmic contacts. Due to the deepening of the interface into the bulk of the semiconductor, the effect of the silicon surface state on parameters of ohmic contacts decreases. As a result their necessary stability and reproducibility are ensured.

The Structure and Properties of MoSi2 Thin Film in Mos Process

1980 ◽  
Vol 38 ◽  
pp. 326-327
Author(s):  
C.K. Wu ◽  
P. Chang ◽  
N. Godinho
Keyword(s):  
Thin Film ◽  
Integrated Circuits ◽  
High Performance ◽  
Large Scale ◽  
Process Development ◽  
Structure And Properties ◽  
Metal Silicides ◽  
High Oxidation ◽  
Important Approach ◽  
High Oxidation Resistance

Recently, the use of refractory metal silicides as low resistivity, high temperature and high oxidation resistance gate materials in large scale integrated circuits (LSI) has become an important approach in advanced MOS process development (1). This research is a systematic study on the structure and properties of molybdenum silicide thin film and its applicability to high performance LSI fabrication.

Inlaid Copper Multilevel Interconnections Using Planarization by Chemical-Mechanical Polishing

MRS Bulletin ◽  
1993 ◽  
Vol 18 (6) ◽  
pp. 46-51 ◽  
Author(s):  
S.P. Murarka ◽  
J. Steigerwald ◽  
R.J. Gutmann
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Ohmic Contacts ◽  
Access Time ◽  
Gigascale Integration ◽  
Interlayer Dielectric ◽  
Application Specific Integrated Circuits ◽  
Large Scale Integration ◽  
Scale Integration ◽  
Application Specific

Continuing advances in the fields of very-large-scale integration (VLSI), ultralarge-scale integration (ULSI), and gigascale integration (GSI), leading to the continuing development of smaller and smaller devices, have continually challenged the fields of materials, processes, and circuit designs. The existing metallization schemes for ohmic contacts, gate metal, and interconnections are inadequate for the ULSI and GSI era. An added concern is the reliability of aluminum and its alloys as the current carrier. Also, the higher resistivity of Al and its use in two-dimensional networks have been considered inadequate, since they lead to unacceptably high values of the so-called interconnection delay or RC delay, especially in microprocessors and application-specific integrated circuits (ICs). Here, R refers to the resistance of the interconnection and C to the total capacitance associated with the interlayer dielectric. For the fastest devices currently available and faster ones of the future, the RC delay must be reduced to such a level that the contribution of RC to switching delays (access time) becomes a small fraction of the total, which is a sum of the inherent device delay associated with the semiconductor, the device geometry and type, and the RC delay.

Industrial Perspective on Reliability of VLSI Devices

1991 ◽  
Vol 225 ◽  
Author(s):  
P. B. Ghate
Keyword(s):  
Integrated Circuits ◽  
Failure Rate ◽  
Large Scale ◽  
Semiconductor Industry ◽  
Test Methods ◽  
Lessons Learned ◽  
Limiting Factors ◽  
Current Status ◽  
Test Procedures ◽  
Process Reliability

ABSTRACTThe reliability of silicon integrated circuits (ICs) has improved significantly in the last decade. The complexity of ICs continues to increase. The semiconductor industry is actively working to a) improve the reliability of very large scale (VLSI) ICs, and b) reduce the failure rates to a value closer to 0.1 FIT by the year 2000. This paper summarizes the current status of quality and reliability of ICs. Some of the reliability limiting factors are described. Inadequacy of conventional accelerated test methods to verify the reliability of VLSI devices is highlighted. A challenging VLSI reliability goal with a failure rate approaching 0.1 FIT requires a) an understanding of the root causes of failure mechanisms, b) a translation of the lessons learned into a set of design rules for the circuit designers, c) appropriate materials and process specifications consistent with manufacturing capabilities, and d) in-process reliability test structures and test procedures. A VLSI failure rate goal of 0.1 FIT presents an exciting challenge for the materials scientists.

Contact Resistance and Methods for its Determination

1982 ◽  
Vol 18 ◽  
Author(s):  
S. Simon Cohen
Keyword(s):  
Integrated Circuits ◽  
Contact Resistance ◽  
Large Scale ◽  
Ohmic Contacts ◽  
Vlsi Circuits ◽  
Single Element ◽  
Large Scale Integration ◽  
Proper Definition ◽  
Definition Of ◽  
Scale Integration

The problem of low resistance ohmic contacts to silicon has been of considerable technological interest. In recent years this problem has received special attention owing to the effect of scaling in very-large-scale integration (VLSI) technology. The field of ohmic contacts to semiconductors comprises two independent parts. First there exists the material science aspect. The choice of a suitable metallization system, the proper semiconductor parameters and the method of the contact formation is not obvious. Then there is the question of the proper definition of the contact resistance and the way it is measured.Several methods for contact resistance determination have been introduced in the past. All seem to have some drawbacks that either limit their usefulness or raise doubts as to their validity in certain situations. We shall discuss the two-, three- and four-terminal resistor methods of measurement. Relevant theoretical considerations will also be included.For conventional integrated circuits with a moderate junction depth of 1–2 μm, aluminum is uniquely suited as a single-element metallization system. However, for VLSI applications it may become obsolete because of several well-defined metallurgical problems. Thus, other metallization systems have to be investigated. We shall briefly discuss some recent data on several other metallization systems. Finally, the problem of size effects on the contact resistance will be discussed. Recent experimental results suggest important clues regarding the development of alternative metallization systems for VLSI circuits and also point to revisions of estimates of achievable design rules.

The Challenge of GaAs Heterojunction Bipolar Transistor Integrated Circuit Technology.

1988 ◽  
Vol 144 ◽  
Author(s):  
Han-Tzong Yuan
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
Large Scale ◽  
Ohmic Contacts ◽  
Bipolar Transistors ◽  
Bipolar Transistor ◽  
Heterojunction Bipolar Transistor ◽  
The Status ◽  
Impurity Doping

ABSTRACTThe status and progress of AlGaAs/GaAs heterojunction bipolar transistor integrated circuits are reviewed. The challenge of fabricating large-scale integrated circuits using heterojunction bipolar transistors is discussed. Specifically, the issues related to low defect epitaxial materials, localized impurity doping techniques, simple and reliable ohmic contacts, and multilevel interconnects are examined.

Some applications of electron beam microanalysis techniques in VLSI process evaluation

1983 ◽  
Vol 41 ◽  
pp. 160-161
Author(s):  
Simon Thomas
Keyword(s):  
Integrated Circuits ◽  
Process Evaluation ◽  
Large Scale ◽  
Technology Development ◽  
Analytical Techniques ◽  
Successful Implementation ◽  
Analysis Of Failures ◽  
Characterization Of Materials ◽  
Circuits Vlsi

Trends in the technology development of very large scale integrated circuits (VLSI) have been in the direction of higher density of components with smaller dimensions. The scaling down of device dimensions has been not only laterally but also in depth. Such efforts in miniaturization bring with them new developments in materials and processing. Successful implementation of these efforts is, to a large extent, dependent on the proper understanding of the material properties, process technologies and reliability issues, through adequate analytical studies. The analytical instrumentation technology has, fortunately, kept pace with the basic requirements of devices with lateral dimensions in the micron/ submicron range and depths of the order of nonometers. Often, newer analytical techniques have emerged or the more conventional techniques have been adapted to meet the more stringent requirements. As such, a variety of analytical techniques are available today to aid an analyst in the efforts of VLSI process evaluation. Generally such analytical efforts are divided into the characterization of materials, evaluation of processing steps and the analysis of failures.

Electron microscopy study of reactively sputter-deposited Ti/N films on silicon

1992 ◽  
Vol 50 (2) ◽  
pp. 1362-1363
Author(s):  
V. C. Kannan ◽  
A. K. Singh ◽  
R. B. Irwin ◽  
S. Chittipeddi ◽  
F. D. Nkansah ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Hexagonal Phase ◽  
Microscopy Study ◽  
Electron Microscopy Study ◽  
Process Conditions ◽  
Tin Films ◽  
Wide Range ◽  
Fcc Phase ◽  
Circuits Vlsi

Titanium nitride (TiN) films have historically been used as diffusion barrier between silicon and aluminum, as an adhesion layer for tungsten deposition and as an interconnect material etc. Recently, the role of TiN films as contact barriers in very large scale silicon integrated circuits (VLSI) has been extensively studied. TiN films have resistivities on the order of 20μ Ω-cm which is much lower than that of titanium (nearly 66μ Ω-cm). Deposited TiN films show resistivities which vary from 20 to 100μ Ω-cm depending upon the type of deposition and process conditions. TiNx is known to have a NaCl type crystal structure for a wide range of compositions. Change in color from metallic luster to gold reflects the stabilization of the TiNx (FCC) phase over the close packed Ti(N) hexagonal phase. It was found that TiN (1:1) ideal composition with the FCC (NaCl-type) structure gives the best electrical property.

TEM study of Cosi2 formation via annealing of Co-Ti bilayers on Si

1995 ◽  
Vol 53 ◽  
pp. 464-465
Author(s):  
N. David Theodore ◽  
Andre Vantomme ◽  
Peter Crazier
Keyword(s):  
Thermal Instability ◽  
Lattice Mismatch ◽  
Field Effect Transistors ◽  
Contact Layer ◽  
Interface Roughness ◽  
Oxide Semiconductor ◽  
Surface Layers ◽  
Silicide Layer ◽  
Small Lattice ◽  
Buried Layers

Contact is typically made to source/drain regions of metal-oxide-semiconductor field-effect transistors (MOSFETs) by use of TiSi2 or CoSi2 layers followed by AI(Cu) metal lines. A silicide layer is used to reduce contact resistance. TiSi2 or CoSi2 are chosen for the contact layer because these silicides have low resistivities (~12-15 μΩ-cm for TiSi2 in the C54 phase, and ~10-15 μΩ-cm for CoSi2). CoSi2 has other desirable properties, such as being thermally stable up to >1000°C for surface layers and >1100°C for buried layers, and having a small lattice mismatch with silicon, -1.2% at room temperature. During CoSi2 growth, Co is the diffusing species. Electrode shorts and voids which can arise if Si is the diffusing species are therefore avoided. However, problems can arise due to silicide-Si interface roughness (leading to nonuniformity in film resistance) and thermal instability of the resistance upon further high temperature annealing. These problems can be avoided if the CoSi2 can be grown epitaxially on silicon.

TEM characterization of WSix films

1994 ◽  
Vol 52 ◽  
pp. 848-849
Author(s):  
V. C. Kannan ◽  
S. M. Merchant ◽  
R. B. Irwin ◽  
A. K. Nanda ◽  
M. Sundahl ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Vapor Deposition ◽  
High Purity ◽  
Physical Vapor Deposition ◽  
Thermal Treatments ◽  
Rapid Thermal Anneal ◽  
Tungsten Silicide ◽  
Tem Characterization ◽  
Metal Silicides

Metal silicides such as WSi2, MoSi2, TiSi2, TaSi2 and CoSi2 have received wide attention in recent years for semiconductor applications in integrated circuits. In this study, we describe the microstructures of WSix films deposited on SiO2 (oxide) and polysilicon (poly) surfaces on Si wafers afterdeposition and rapid thermal anneal (RTA) at several temperatures. The stoichiometry of WSix films was confirmed by Rutherford Backscattering Spectroscopy (RBS). A correlation between the observed microstructure and measured sheet resistance of the films was also obtained.WSix films were deposited by physical vapor deposition (PVD) using magnetron sputteringin a Varian 3180. A high purity tungsten silicide target with a Si:W ratio of 2.85 was used. Films deposited on oxide or poly substrates gave rise to a Si:W ratio of 2.65 as observed by RBS. To simulatethe thermal treatments of subsequent processing procedures, wafers with tungsten silicide films were subjected to RTA (AG Associates Heatpulse 4108) in a N2 ambient for 60 seconds at temperatures ranging from 700° to 1000°C.

Characterization of Interconnect Defects Using Scanning Thermal Conductivity Microscopy

2004 ◽  
Author(s):  
H.W. Ho ◽  
J.C.H. Phang ◽  
A. Altes ◽  
L.J. Balk
Keyword(s):  
Thermal Conductivity ◽  
Integrated Circuits ◽  
Large Scale

Abstract In this paper, scanning thermal conductivity microscopy is used to characterize interconnect defects due to electromigration. Similar features are observed both in the temperature and thermal conductivity micrographs. The key advantage of the thermal conductivity mode is that specimen bias is not required. This is an important advantage for the characterization of defects in large scale integrated circuits. The thermal conductivity micrographs of extrusion, exposed and subsurface voids are presented and compared with the corresponding topography and temperature micrographs.

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