The Challenge of GaAs Heterojunction Bipolar Transistor Integrated Circuit Technology.

1988 ◽  
Vol 144 ◽  
Author(s):  
Han-Tzong Yuan
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
Large Scale ◽  
Ohmic Contacts ◽  
Bipolar Transistors ◽  
Bipolar Transistor ◽  
Heterojunction Bipolar Transistor ◽  
The Status ◽  
Impurity Doping

ABSTRACTThe status and progress of AlGaAs/GaAs heterojunction bipolar transistor integrated circuits are reviewed. The challenge of fabricating large-scale integrated circuits using heterojunction bipolar transistors is discussed. Specifically, the issues related to low defect epitaxial materials, localized impurity doping techniques, simple and reliable ohmic contacts, and multilevel interconnects are examined.

TEM study of phosphorus-implanted pseudomorphic Si0.88Ge0.12 on Si(100)

1995 ◽  
Vol 53 ◽  
pp. 468-469
Author(s):  
N. David Theodore ◽  
Donald Y.C Lie ◽  
J. H. Song ◽  
Peter Crozier
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
High Speed ◽  
Room Temperature ◽  
Strain Relaxation ◽  
Bipolar Transistors ◽  
Sige Hbt ◽  
Integrated Circuit Manufacturing ◽  
Microstructural Behavior

SiGe is being extensively investigated for use in heterojunction bipolar-transistors (HBT) and high-speed integrated circuits. The material offers adjustable bandgaps, improved carrier mobilities over Si homostructures, and compatibility with Si-based integrated-circuit manufacturing. SiGe HBT performance can be improved by increasing the base-doping or by widening the base link-region by ion implantation. A problem that arises however is that implantation can enhance strain-relaxation of SiGe/Si.Furthermore, once misfit or threading dislocations result, the defects can give rise to recombination-generation in depletion regions of semiconductor devices. It is of relevance therefore to study the damage and anneal behavior of implanted SiGe layers. The present study investigates the microstructural behavior of phosphorus implanted pseudomorphic metastable Si0.88Ge0.12 films on silicon, exposed to various anneals.Metastable pseudomorphic Si0.88Ge0.12 films were grown ~265 nm thick on a silicon wafer by molecular-beam epitaxy. Pieces of this wafer were then implanted at room temperature with 100 keV phosphorus ions to a dose of 1.5×1015 cm-2.

SILICON:GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTORS: FROM EXPERIMENT TO TECHNOLOGY

1994 ◽  
Vol 05 (03) ◽  
pp. 473-491 ◽  
Author(s):  
B.S. MEYERSON ◽  
D.L. HARAME ◽  
J. STORK ◽  
E. CRABBE ◽  
J. COMFORT ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
Film Growth ◽  
Bipolar Transistors ◽  
Heterojunction Bipolar Transistor ◽  
Thin Film Growth ◽  
Sige Hbt ◽  
Digital To Analog Converters ◽  
Silicon Epitaxy ◽  
Scale Integration

Recent advances in thin film growth techniques, notably the maturation of low temperature silicon epitaxy, have enabled the routine fabrication of highly controlled dopant and silicon:germanium alloy profiles. These capabilities, combined with refinements in heterojunction bipolar transistor designs, have led to the first integrated circuits in the silicon:germanium materials system. Utilizing a commercial (Leybold-AG) UHVCVD tool for SiGe epitaxy on a standard 8" CMOS line, medium scale integration has been achieved, with the first IC components being SiGe HBT based 1 Ghz, 12 bit, digital to analog converters.

scholarly journals Investigation of the static current gain for InP/InGaAs single heterojunction bipolar transistor

2019 ◽  
Vol 13 (3) ◽  
pp. 1345
Author(s):  
Jihane Ouchrif ◽  
Abdennaceur Baghdad ◽  
Aicha Sshel ◽  
Abdelmajid Badri ◽  
Abdelhakim Ballouk
Keyword(s):  
Heterojunction Bipolar Transistors ◽  
Communication Systems ◽  
Bipolar Transistors ◽  
Bipolar Transistor ◽  
Heterojunction Bipolar Transistor ◽  
Current Gain ◽  
Technological Parameters ◽  
Device Structure ◽  
Optimal Values ◽  
Output Characteristics

<p>Heterojunction Bipolar Transistors are being used increasingly in communication systems due to their electrical performances. They are considered as excellent electronic devices. This paper presents an investigation of the static current gain β based on two technological parameters related to the device geometry for InP/InGaAs Single Heterojunction Bipolar Transistor (SHBT). These parameters are the base width  and the emitter length . We used Silvaco’s TCAD tools to design the device structure, and to extract the static current gain β from I-V output characteristics figures. According to this investigation, we determined the optimal values of the examined parameters which allow obtaining the highest static current gain β.</p>

Fabrication, Performance, and Reliability of InP-Based HBTs

1993 ◽  
Vol 300 ◽  
Author(s):  
William E. Stanchina ◽  
Robert A. Metzger ◽  
Joseph F. Jensen ◽  
Madjid Hafizi ◽  
David B. Rensch
Keyword(s):  
Indium Phosphide ◽  
Indium Arsenide ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
Material Properties ◽  
Bipolar Transistors ◽  
Gallium Indium Arsenide ◽  
The Past ◽  
The Status ◽  
Performance Results

ABSTRACTOver the past 10 years, heterojunction bipolar transistors (HBTs) have progressed to where integrated circuit (IC) products are being sold and foundry services are being commercially offered utilizing gallium arsenide (GaAs) based technology. We will discuss, here, an alternative HBT technology based on indium phosphide (InP). While this technology is less mature than its GaAs counterpart, it offers several attractive benefits in comparison with GaAs. These benefits are provided through several key material properties of InP and ternary compound semiconductors, eg. gallium indium arsenide (GaInAs), grown on the InP. We review the status of this npn HBT technology and present performance results which illustrate the benefits of the technology with respect to electronic applications. Finally, we present measured reliability data for this technology which shows outstanding projected lifetimes.

ULTRAHIGH fmax AlInAs/GaInAs TRANSFERRED-SUBSTRATE HETEROJUNCTION BIPOLAR TRANSISTORS FOR INTEGRATED CIRCUITS APPLICATIONS

1998 ◽  
Vol 09 (02) ◽  
pp. 643-670 ◽  
Author(s):  
BIPUL AGARWAL ◽  
RAJASEKHAR PULLELA ◽  
UDDALAK BHATTACHARYA ◽  
DINO MENSA ◽  
QING-HUNG LEE ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
High Speed ◽  
Bipolar Transistors ◽  
Fabrication Process ◽  
Material System ◽  
Rf Performance ◽  
Consequent Increase ◽  
Very High

Transferred-substrate heterojunction bipolar transistors (HBTs) have demonstrated very high bandwidths and are potential candidates for very high speed integrated circuit (IC) applications. The transferred-substrate process permits fabrication of narrow and aligned emitter-base and collector-base junctions, reducing the collector-base capacitance and increasing the device f max . Unlike conventional double-mesa HBTs, transferred-substrate HBTs can be scaled to submicron dimensions with a consequent increase in bandwidth. This paper introduces the concept of transferred-substrate HBTs. Fabrication process in the AlInAs/GaInAs material system is presented, followed by DC and RF performance. A demonstration IC is shown along with some integrated circuits in development.

Inlaid Copper Multilevel Interconnections Using Planarization by Chemical-Mechanical Polishing

MRS Bulletin ◽  
1993 ◽  
Vol 18 (6) ◽  
pp. 46-51 ◽  
Author(s):  
S.P. Murarka ◽  
J. Steigerwald ◽  
R.J. Gutmann
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Ohmic Contacts ◽  
Access Time ◽  
Gigascale Integration ◽  
Interlayer Dielectric ◽  
Application Specific Integrated Circuits ◽  
Large Scale Integration ◽  
Scale Integration ◽  
Application Specific

Continuing advances in the fields of very-large-scale integration (VLSI), ultralarge-scale integration (ULSI), and gigascale integration (GSI), leading to the continuing development of smaller and smaller devices, have continually challenged the fields of materials, processes, and circuit designs. The existing metallization schemes for ohmic contacts, gate metal, and interconnections are inadequate for the ULSI and GSI era. An added concern is the reliability of aluminum and its alloys as the current carrier. Also, the higher resistivity of Al and its use in two-dimensional networks have been considered inadequate, since they lead to unacceptably high values of the so-called interconnection delay or RC delay, especially in microprocessors and application-specific integrated circuits (ICs). Here, R refers to the resistance of the interconnection and C to the total capacitance associated with the interlayer dielectric. For the fastest devices currently available and faster ones of the future, the RC delay must be reduced to such a level that the contribution of RC to switching delays (access time) becomes a small fraction of the total, which is a sum of the inherent device delay associated with the semiconductor, the device geometry and type, and the RC delay.

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