scholarly journals Analog Operation Temperature Dependence of nMOS Junctionless Transistors Focusing on Harmonic Distortion

2011 ◽  
Vol 6 (2) ◽  
pp. 114-121
Author(s):  
Rodrigo T. Doria ◽  
Marcelo Antonio Pavanello ◽  
Renan D. Trevisoli ◽  
Michelly De Souza ◽  
Chi-Woo Lee ◽  
...  
Keyword(s):  
Harmonic Distortion ◽  
Drain Current ◽  
Voltage Gain ◽  
Third Order ◽  
Inversion Mode ◽  
Nanowire Transistors ◽  
Operation Temperature ◽  
Analog Performance ◽  
Junctionless Transistors ◽  
Fixed Input

This paper performs a comparative study of the analog performance of Junctionless Nanowire Transistors (JNTs) and classical Trigate inversion mode (IM) devices focusing on the harmonic distortion. The study has been carried out in the temperature range of 223 K up to 473 K. The non-linearity or harmonic distortion (HD) has been evaluated in terms of the total and the third order distortions (THD and HD3, respectively) at a fixed input bias and at a targeted output swing. Several parameters important for the HD evaluation have also been observed such as the transconductance to the drain current ratio (gm/IDS), the Early voltage (VEA) and the intrinsic voltage gain (AV). Trigate devices showed maximum AV around room temperature whereas in JNTs the intrinsic voltage gain increases with the temperature. Due to the different AV characteristics, Junctionless transistors present improved HD at higher temperatures whereas inversion mode Trigate devices show better HD properties at room temperature.When both devices are compared, Junctionless transistors present better THD and HD3 with respect to the IM Trigate devices.

Linearity Analysis of GME-TRC MOSFET Using SiO2 as a Gate Insulator at High Temperature

2013 ◽  
Vol 685 ◽  
pp. 207-210
Author(s):  
Priyanka Malik ◽  
R.S. Gupta ◽  
Mridula Gupta
Keyword(s):  
Drain Current ◽  
Paper Analysis ◽  
Performance Comparison ◽  
Gate Insulator ◽  
Third Order ◽  
Temperature Variations ◽  
Analog Performance ◽  
Recessed Channel ◽  
Bias Point ◽  
The Impact

This paper analysis the impact of temperature variation on gate material engineered trapezoidal recessed channel (GME-TRC) MOSFET and trapezoidal recessed channel (TRC) MOSFET, using ATLAS: 3D device simulator [. The study focuses on the linearity and analog performance comparison of GME-TRC and TRC MOSFETs and the impact of temperature variations on some of the key parameters like drain current, transconductance and the optimum bias point in terms of gm3 (third order derivative of Ids-Vgs) and VIP3 has been analysed.

scholarly journals The Roles of the Gate Bias, Doping Concentration, Temperature and Geometry on the Harmonic Distortion of Junctionless Nanowire Transistors Operating in the Linear Regime

2014 ◽  
Vol 9 (2) ◽  
pp. 110-117
Author(s):  
Rodrigo T. Doria ◽  
Renan D. Trevisoli ◽  
Michelly De Souza ◽  
Magali Estrada ◽  
Antonio Cerdeira ◽  
...  
Keyword(s):  
Experimental Data ◽  
Doping Concentration ◽  
Series Resistance ◽  
Harmonic Distortion ◽  
Physical Parameters ◽  
Gate Bias ◽  
Linear Regime ◽  
Third Order ◽  
Nanowire Transistors ◽  
The Third

The linearity of Junctionless nanowire transistors operating in the linear regime has been evaluated through experimental data and numerical simulations. The influences of the fin width, the gate bias, the temperature, the doping concentration and the geometry on the overall linearity have been evaluated. The increase of the series resistance associated both to the variation of the physical parameters and the incomplete ionization effect has shown to improve the second order distortion and degrade the third order one.

scholarly journals Influence of Fin Shape and Temperature on Conventional and Strained MuGFETs’ Analog Parameters

2011 ◽  
Vol 6 (2) ◽  
pp. 94-101
Author(s):  
Rudolf T. Buhler ◽  
Renato Giacomini ◽  
João Antonio Martino
Keyword(s):  
Harmonic Distortion ◽  
Drain Current ◽  
Strained Silicon ◽  
Voltage Gain ◽  
Unity Gain ◽  
Voltage Saturation ◽  
Body Cross Section ◽  
Rectangular Body ◽  
Analog Parameters ◽  
Fin Shape

This work evaluates two important technological variations of Triple-Gate FETs: the use of strained silicon and the occurrence of non-rectangular body cross-section. The anaysis is focused on the electrical parameters for analog applications, and covers a temperature range from 150 K to 400 K. The comparison of the intrinsic voltage gain between the different trapezoidal fin shapes showed that the fin shape can have a major role in some analog parameters than the use of the strained silicon technology, helping to improve those parameters under certain circumstances. The highest intrinsic voltage gains were obtained for strained devices with top fin width larger than bottom at low temperature. Besides the intrinsic voltage gain, were also studied: the threshold voltage, subthreshold swing, drain induced barrier lowering, channel resistance, total harmonic distortion, transconductance, transconductance to drain current ratio, output conductance, Early voltage, drain voltage saturation and unity gain frequency.

Second- and third-order harmonic distortion in DFB lasers

1995 ◽  
Vol 31 (11) ◽  
pp. 1974-1980 ◽  
Author(s):  
Liming Zhang ◽  
D.A. Ackerman
Keyword(s):  
Harmonic Distortion ◽  
Third Order

scholarly journals Design and Analysis of a Repetitive Current Controller for a Single-Phase Bridgeless SEPIC PFC Converter

Energies ◽  
2018 ◽  
Vol 12 (1) ◽  
pp. 131 ◽  
Author(s):  
Jinwoo Kim ◽  
Sanghun Han ◽  
Wontae Cho ◽  
Younghoon Cho ◽  
Hyunsoo Koh
Keyword(s):  
Controller Design ◽  
Harmonic Distortion ◽  
Input Current ◽  
Order Model ◽  
Third Order ◽  
Current Controller ◽  
The Stability ◽  
Small Signal Modeling ◽  
Fifth Order ◽  
Repetitive Controller

This paper studies a repetitive controller design scheme for a bridgeless single-ended primary inductor converter (SEPIC) power factor correction (PFC) converter to mitigate input current distortions. A small signal modeling of the converter is performed by a fifth-order model. Since the fifth-order model is complex to be applied in designing a current controller, the model is approximated to a third-order model. Using the third-order model, the repetitive controller is designed to reduce the input current distortion. Then, the stability of the repetitive controller is verified with an error transfer function. The proposed controller performance is validated by simulation, and the experiment results show that the input current total harmonic distortion (THD) is improved by applying the proposed controller for an 800 W bridgeless SEPIC PFC converter prototype.

Analytical Drain Current Compact Model in the Depletion Operation Region of Short-Channel Triple-Gate Junctionless Transistors

2017 ◽  
Vol 64 (1) ◽  
pp. 66-72 ◽  
Author(s):  
Theodoros A. Oproglidis ◽  
Andreas Tsormpatzoglou ◽  
Dimitrios H. Tassis ◽  
Theano A. Karatsori ◽  
Sylvain Barraud ◽  
...  
Keyword(s):  
Drain Current ◽  
Compact Model ◽  
Short Channel ◽  
Junctionless Transistors

Junctionless nanowire transistors parameters extraction based on drain current measurements

2019 ◽  
Vol 158 ◽  
pp. 37-45
Author(s):  
Renan Trevisoli ◽  
Rodrigo T. Doria ◽  
Michelly de Souza ◽  
Sylvain Barraud ◽  
Marcelo A. Pavanello
Keyword(s):  
Drain Current ◽  
Nanowire Transistors ◽  
Parameters Extraction

scholarly journals A new assessment method of pHEMT models by comparing relative errors of drain current and its derivatives up to the third order

2017 ◽  
Vol 198 ◽  
pp. 012004
Author(s):  
Josef Dobeš ◽  
Martin Grábner ◽  
Pavel Puričer ◽  
František Vejražka ◽  
Jan Míchal ◽  
...  
Keyword(s):  
Drain Current ◽  
Assessment Method ◽  
Third Order ◽  
The Third ◽  
Relative Errors
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