Application of Focused Ion Beam System as A Defect Localization and Root Cause Analysis Tool

Author(s):  
C.C. Ooi ◽  
K.H. Siek ◽  
K.S. Sim

Abstract Focused ion beam system has been widely used as a critical failure analysis tool as microprocessor technology advances at a ramping speed. It has become an essential step in failure analysis to reveal physical defects post electrical fault isolation. In this highly competitive and challenging environment prevalent today, failure analysis throughput time is of utmost important. Therefore quick, efficient and reliable physical failure analysis technique is needed to avoid potential issues from becoming bigger. This paper will discuss the applications of FIB as a defect localization and root cause determination tool through the passive charge contrast technique and pattern FIB analysis.

Author(s):  
P. Tangyunyong ◽  
A.Y. Liang ◽  
A.W. Righter ◽  
D.L. Barton ◽  
J.M. Soden

Abstract Fluorescent microthermal imaging (FMI) involves coating a sample surface with a thin fluorescent film that, upon exposure to UV light source, emits temperature-dependent fluorescence [1-7]. The principle behind FMI was thoroughly reviewed at the ISTFA in 1994 [8, 9]. In two recent publications [10,11], we identified several factors in film preparation and data processing that dramatically improved the thermal resolution and sensitivity of FMI. These factors include signal averaging, the use of base mixture films, film stabilization and film curing. These findings significantly enhance the capability of FMI as a failure analysis tool. In this paper, we show several examples that use FMI to quickly localize heat-generating defects ("hot spots"). When used with other failure analysis techniques such as focused ion beam (FIB) cross sectioning and scanning electron microscope (SEM) imaging, we demonstrate that FMI is a powerful tool to efficiently identify the root cause of failures in complex ICs. In addition to defect localization, we use a failing IC to determine the sensitivity of FMI (i.e., the lowest power that can be detected) in an ideal situation where the defects are very localized and near the surface.


2015 ◽  
Vol 2015 (1) ◽  
pp. 000469-000473 ◽  
Author(s):  
J. Gaudestad ◽  
A. Orozco ◽  
I. De Wolf ◽  
T. Wang ◽  
T. Webers ◽  
...  

In this paper we show an efficient workflow that combines Magnetic Field Imaging (MFI) and Dual Beam Plasma Focused Ion Beam (DB-PFIB) for fast and efficient Fault Isolation and root cause analysis in 2.5/3D devices. The work proves MFI is the best method for Electric Fault Isolation (EFI) of short failures in 2.5/3D Through Silicon Via (TSV) triple stacked devices in a true non-destructive way by imaging the current path. To confirm the failing locations and to do Physical Failure Analysis (PFA), a DB-PFIB system was used for cross sectioning and volume analysis of the TSV structures and high resolution imaging of the identified defects. With a DB-PFIB, the fault is exposed and analyzed without any sample prep artifacts seen in mechanical polishing or laser preparation techniques and done in a considerably shorter amount of time than that required when using a traditional Gallium Focused Ion Beam (FIB).


Author(s):  
Hung Chin Chen ◽  
Chih Yang Tsai ◽  
Shih Yuan Liu ◽  
Yu Pang Chang ◽  
Jian Chang Lin

Abstract Fault isolation is the most important step for Failure Analysis (FA), and it is closely linked with the success rate of failure mechanism finding. In this paper, we will introduce a case that hard to debug with traditional FA skills. In order to find out its root cause, several advanced techniques such as layout tracing, circuit edit and Infrared Ray–Optical Beam Induced Resistance Change (IR-OBIRCH) analysis had been applied. The circuit edit was performed following layout tracing for depositing probing pads by Focused Ion Beam (FIB). Then, IR-OBIRCH analysis with biasing on the two FIB deposited probing pads and a failure location was detected. Finally, the root cause of inter- metal layer bridge was found in subsequent physical failure analysis.


Author(s):  
J. Gaudestad ◽  
A. Orozco ◽  
I. De Wolf ◽  
T. Wang ◽  
T. Webers ◽  
...  

Abstract In this paper we show an efficient workflow that combines Magnetic Field Imaging (MFI) and Dual Beam Plasma Focused Ion Beam (DB-PFIB) for fast and efficient Fault Isolation and root cause analysis in 2.5/3D devices. The work proves MFI is the best method for Electric Fault Isolation (EFI) of short failures in 2.5/3D Through Silicon Via (TSV) triple stacked devices in a true non-destructive way by imaging the current path. To confirm the failing locations and to do Physical Failure Analysis (PFA), a DB-PFIB system was used for cross sectioning and volume analysis of the TSV structures and high resolution imaging of the identified defects. With a DB-PFIB, the fault is exposed and analyzed without any sample prep artifacts seen in mechanical polishing or laser preparation techniques and done in a considerably shorter amount of time than that required when using a traditional Gallium Focused Ion Beam (FIB).


Author(s):  
Jane Y. Li ◽  
Chuan Zhang ◽  
John Aguada ◽  
Christopher Nemirow ◽  
Howard Marks

Abstract This paper demonstrates a methodology for chip level defect localization that allows complex logic nets to be approached from multiple perspectives during failure analysis of modern flip-chip CMOS IC devices. By combining chip backside deprocessing with site-specific plasma Focused Ion Beam (pFIB) low angle milling, the area of interest in a failure IC device is made accessible from any direction for nanoprobing and Electron Beam Absorbed Current (EBAC) analysis. This methodology allows subtle defects to be more accurately localized and analyzed for thorough root-cause understanding.


Author(s):  
Liang Hong ◽  
Jia Li ◽  
Haifeng Wang

Abstract This paper provides an innovative root cause failure analysis method that combines multiple failure analysis (FA) techniques to narrow down and expose the shorting location and allow the material analysis of the shorting defect. It begins with a basic electrical testing to narrow down shorting metal layers, then utilizing mechanical lapping to expose over coat layers. This is followed by optical beam induced resistance change imaging to further narrow down the shorting location. Scanning electron microscopy and optical imaging are used together with focused ion beam milling to slice and view through the potential shorting area until the shorting defect is exposed. Finally, transmission electron microscopy (TEM) sample is prepared, and TEM analysis is carried out to pin point the root cause of the shorting. This method has been demonstrated successfully on Western Digital inter-metal layers shorting FA.


2018 ◽  
Author(s):  
Sze Yee Tan ◽  
Chiu Soon Wong ◽  
Chea Wee Lo ◽  
Cin Sheng Goh

Abstract In the back-end assembly process, all of the packages will be tested prior to disposition to the customers in order to filter out any device with failure. For a reject unit with an unknown failure mechanism, it will be subjected to a comprehensive failure analysis (FA) to identify the root cause of the failure. Non-destructive verification, following by front-side decapsulation and internal physical inspection is the common way to visualise and identify the physical defect that usually causes the failure of a device during the back-end assembly process. For certain failures, visualization of the defect might not be straight forward after the decapsulation because the defect may be embedded or buried underneath a layer or wedge bond on the die. In this case, a more complicated FA analysis flow which comprises various precision techniques such as parallel lapping, hotspot localisation and focused-ion-beam (FIB) analyses will be needed to thin down the top layer/wedge bond for a precise localisation of the defect prior to precision analysis by FIB. However, the process to thin down the top layer/wedge bond with an exposed die of a partially decapsulated package is a tricky job as artefacts such as crack/scratches on die are likely to be introduced during the process of polishing. Also it is relatively difficult to control the thickness and levelling of the top layer/wedge bond during the thinning process. In this work, we developed a method that allows the analyst to re-cap the partially decapped package, and also to precisely measure and thin down the top layer to an accuracy of less than < 2um without the introduction of artefacts.


Author(s):  
Frank Altmann ◽  
Matthias Petzold ◽  
Christian Schmidt ◽  
Roland Salzer ◽  
Cathal Cassidy ◽  
...  

Abstract In this paper we will introduce novel methodical approaches for material and failure analysis of 3D integrated devices. The potential and advantages of the new concepts and tools will be demonstrated for flip-chip-like interconnects but in addition, for the first time, for Through Silicon Vias (TSV). The employed techniques combine non-destructive fault localization with efficient and accurate target preparation to get access for following microstructure diagnostics, forming a subsequent failure analysis workflow. The concept presented here involves the application of improved Lock-In Thermography (LIT), and three different innovative concepts of high rate Focused Ion Beam (FIB) techniques.


Author(s):  
Fayik M. Bundhoo ◽  
Soundaranathan Kasivisvanatha

Abstract A novel failure analysis approach has been developed to isolate and characterize deep sub micron defects in P<100>- silicon lattice. This technique utilizes unique wet chemical deprocessing and side wall cleaning in conjunction with focused ion beam milling to isolate a single vertical failing DMOS source contact from a parallel array of 462K contacts covered with oxide dielectric and top metal layers. The two methods of analysis and root cause of crystalline lattice dislocation in a vertical DMOS transistor are discussed. TEM examination of implanted dopant interface was carried out in order to determine the nature and origin of lattice dislocations. A study1 indicates that lattice dislocations are generated by deep boron and arsenic implants that are not adequately annealed. In our analysis, these dislocations were observed as loop pairs causing low-level leakage that did not initially allow the part to fail. However, these silicon lattice dislocations do pose reliability issues.


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