N-Channel Sub-Threshold Leakage “Pipes” Generated From Micro-Twinning Near Shallow Trench Isolation Interface

ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2002p0599 ◽

2002 ◽

Author(s):

Erick M. Spory

Keyword(s):

Compressive Stress ◽

Process Parameters ◽

Shallow Trench Isolation ◽

Silicon Lattice ◽

Corner Region ◽

Twin Defect ◽

Close Proximity ◽

Trench Isolation ◽

Pipe Formation ◽

Very High

Abstract The pursuit of shorter and narrower channel transistor processes, especially those employing Shallow Trench Isolation (STI), can readily produce devices that are increasingly susceptible to the formation of sub-threshold, leakage-generating defects. Specifically, STI N-channel devices exhibiting lengths at or below 0.35 um and with widths below 1 um, are at a heightened risk of developing a channel micro-twin defect “pipe” due to the very high compressive stress within the silicon lattice. Wider, sub-0.35 um devices can also exhibit the problem if their channels are in extremely close proximity to an active/STI corner region. Modification of the relevant process parameters can significantly alleviate this stress and reduce the frequency of “pipe” formation.

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Pattern density effects in fixed abrasive polishing

MRS Proceedings ◽

10.1557/proc-732-i12.3 ◽

2002 ◽

Vol 732 ◽

Author(s):

Rajasekhar Venigalla ◽

Laertis Economikos ◽

S.V. Babu

Keyword(s):

Chemical Mechanical Planarization ◽

High Rate ◽

Shallow Trench Isolation ◽

Density Effects ◽

Pattern Density ◽

Aggressive Action ◽

Trench Isolation ◽

Fixed Abrasive Pad ◽

Fixed Abrasive ◽

Very High

AbstractWe investigated pattern density effects during chemical mechanical planarization (CMP) for shallow trench isolation (STI) applications using fixed abrasive pads to better control the fixed abrasive polishing process. We observed that the polishing characteristics of higher pattern density features are strongly dependent on the presence of lower pattern density features on the same die in the wafer. This has been attributed to the aggressive action of lower pattern density features on the fixed abrasive pad which results in a more effective activation of the pad by them. Thus even the 100% pattern density features are initially polished at a very high rate when lower density features are present.

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A Silicon Nitride Based Shallow Trench Isolation with Side-Gate for CMOS Integration with MEMS Components for System-On-Chip Applications

MRS Proceedings ◽

10.1557/proc-833-g6.9 ◽

2004 ◽

Vol 833 ◽

Cited By ~ 1

Author(s):

Ali Gokirmak ◽

Sandip Tiwari

Keyword(s):

Silicon Nitride ◽

System On Chip ◽

Leakage Currents ◽

Shallow Trench Isolation ◽

Mems Resonators ◽

High Temperature Anneal ◽

Close Proximity ◽

Trench Isolation ◽

Electrostatic Control ◽

On Chip

ABSTRACTWe have developed a hydrofluoric acid (HF) resistant, composite shallow trench isolation (STI) process for MOSFETs utilizing silicon nitride as isolation material for on-chip integration of micro-electro-mechanical (MEMS) resonators and CMOS devices. Peripheral leakage currents in silicon nitride isolated MOSFETs are suppressed by employing an independently controlled polysilicon side-gate, surrounding the active area of the devices. Electrostatic control of the threshold voltage at the device periphery alleviates the need for edge implants, resulting in increased thermal budget. Compatibility with HF release processes and high temperature anneal cycles allows integration of MEMS components in close proximity to CMOS devices for system-on-chip applications. nMOSFET devices fabricated using this composite STI process show excellent device characteristics.

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Micro-Raman Spectroscopy Evaluation of the Local Mechanical Stress in Shallow Trench Isolation CMOS Structures: Correlation with Defect Generation and Diode Leakage

10.31399/asm.cp.istfa1998p0011 ◽

1998 ◽

Author(s):

I. De Wolf ◽

G. Groeseneken ◽

H.E. Maes ◽

M. Bolt ◽

K. Barla ◽

...

Keyword(s):

Raman Spectroscopy ◽

Mechanical Stress ◽

Defect Formation ◽

Active Area ◽

Wet Oxidation ◽

Leakage Currents ◽

Shallow Trench Isolation ◽

Micro Raman Spectroscopy ◽

Silicon Devices ◽

Trench Isolation

Abstract It is shown, using micro-Raman spectroscopy, that Shallow Trench Isolation introduces high stresses in the active area of silicon devices when wet oxidation steps are used. These stresses result in defect formation in the active area, leading to high diode leakage currents. The stress levels are highest near the outer edges of line structures and at square structures. They also increase with decreasing active area dimensions.

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Fabricating high performance n-channel lateral double diffused metal–oxide–semiconductor transistors utilizing the shallow trench isolation as a salicide blocking mask of the drift region

Current Applied Physics ◽

10.1016/j.cap.2007.10.086 ◽

2009 ◽

Vol 9 (1) ◽

pp. 9-12 ◽

Cited By ~ 3

Author(s):

Kee-Yeol Na ◽

Yeong-Seuk Kim

Keyword(s):

Metal Oxide ◽

High Performance ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Drift Region ◽

Shallow Trench Isolation ◽

Trench Isolation

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Advances in Chemical-Mechanical Planarization

MRS Bulletin ◽

10.1557/mrs2002.244 ◽

2002 ◽

Vol 27 (10) ◽

pp. 743-751 ◽

Cited By ~ 77

Author(s):

Rajiv K. Singh ◽

Rajeev Bajaj

Keyword(s):

Surface Topography ◽

Process Integration ◽

Semiconductor Industry ◽

Chemical Mechanical Planarization ◽

Shallow Trench Isolation ◽

Trench Isolation ◽

Fundamental Understanding ◽

Copper Polishing ◽

Future Growth

AbstractThe primary aim of this issue of MRS Bulletin is to present an overview of the materials issues in chemical–mechanical planarization (CMP), also known as chemical–mechanial polishing, a process that is used in the semiconductor industry to isolate and connect individual transistors on a chip. The CMP process has been the fastest-growing semiconductor operation in the last decade, and its future growth is being fueled by the introduction of copper-based interconnects in advanced microprocessors and other devices. Articles in this issue range from providing a fundamental understanding of the CMP process to the latest advancements in the field. Topics covered in these articles include an overview of CMP, fundamental principles of slurry design, understanding wafer–pad–slurry interactions, process integration issues, the formulation of abrasive-free slurries for copper polishing, understanding surface topography issues in shallow trench isolation, and emerging applications.

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