Failure Analysis of a Transistor Lead

2000 ◽  
Author(s):  
Yasushi Deguchi ◽  
Sumio Matsuda ◽  
Jiro Aoki ◽  
Takashi Tamura ◽  
Yasunobu Iwai ◽  
...  
Keyword(s):  
Sulfuric Acid ◽  
Low Power ◽  
Failure Analysis ◽  
Cross Section ◽  
Focused Ion Beam ◽  
Protective Coatings ◽  
Ion Beam ◽  
Worst Case ◽  
Dissolved Ions ◽  
Plating Layer

Abstract We investigated the cause of the whisker/discoloration which were found in the transistor lead of stocks (package type TO-18, low power use). In process of the investigation, we estimate two corrosion models that the first model is the remnant of sulfuric acid in cracks of the nickel-phosphorus plating layer in the transistor lead, the second model is the out-gassing or the dissolved ions from the stock container and conductive mat. As the results of the investigation which includes analyses of the whisker/discoloration cross section made by FIB (Focused Ion Beam), a reproductive experiment and so on, the whisker/discoloration were the corrosion reacted between the solder (Pb-Sn) on the transistor lead and SO42- ions of the stock container. We estimate that the new corrosion will not occur and grow in mounted devices because of rejecting the source of corrosion (stock containers). Further, in the worst case of the corrosion occurrence, protective coatings were applied to the mounted transistor lead, as the measure against falling away from the transistor lead.

Failure Modes, Reliability Analysis and Case Studies on the Integration of Copper and Low-K Technology

2004 ◽  
Author(s):  
Huixian Wu ◽  
James Cargo ◽  
Huixian Wu ◽  
Marvin White
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Cross Section ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Copper Interconnects ◽  
Wet Chemical ◽  
Low K ◽  
Section Analysis

Abstract The integration of copper interconnects and low-K dielectrics will present novel failure modes and reliability issues to failure analysts. This paper discusses failure modes related to Cu/low-K technology. Here, physical failure analysis (FA) techniques including deprocessing and cross-section analysis have been developed. The deprocessing techniques include wet chemical etching, reactive ion etching, chemical mechanical polishing and a combination of these techniques. Case studies on different failure modes related to Cu/low k technology are discussed: copper voiding, copper extrusion; electromigration stress failure; dielectric cracks; delamination-interface adhesion; and FA on circuit-under-pad. For the cross-section analysis of copper/low-K samples, focused ion beam techniques have been developed. Scanning electron microscopy, EDX, and TEM analytical analysis have been used for failure analysis for Cu/low-K technology. Various failure modes and reliability issues have also been addressed.

Automated Diagonal Slice and View Solution for 3D Device Structure Analysis

2018 ◽  
Author(s):  
Sang Hoon Lee ◽  
Jeff Blackwood ◽  
Stacey Stone ◽  
Michael Schmidt ◽  
Mark Williamson ◽  
...  
Keyword(s):  
Cross Section ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Image Data ◽  
Planar Surface ◽  
Device Structure ◽  
Cross Sectional ◽  
Device Structures ◽  
The Cross ◽  
Planar Analysis

Abstract The cross-sectional and planar analysis of current generation 3D device structures can be analyzed using a single Focused Ion Beam (FIB) mill. This is achieved using a diagonal milling technique that exposes a multilayer planar surface as well as the cross-section. this provides image data allowing for an efficient method to monitor the fabrication process and find device design errors. This process saves tremendous sample-to-data time, decreasing it from days to hours while still providing precise defect and structure data.

Focused Ion Beam Analysis of Low-K Dielectrics

2000 ◽  
Author(s):  
H. J. Bender ◽  
R. A. Donaton
Keyword(s):  
Electron Microscope ◽  
Cross Section ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Single Step ◽  
Specimen Preparation ◽  
Transmission Electron ◽  
Beam Analysis ◽  
Low K ◽  
Scanning Electron

Abstract The characteristics of an organic low-k dielectric during investigation by focused ion beam (FIB) are discussed for the different FIB application modes: cross-section imaging, specimen preparation for transmission electron microscopy, and via milling for device modification. It is shown that the material is more stable under the ion beam than under the electron beam in the scanning electron microscope (SEM) or in the transmission electron microscope (TEM). The milling of the material by H2O vapor assistance is strongly enhanced. Also by applying XeF2 etching an enhanced milling rate can be obtained so that both the polymer layer and the intermediate oxides can be etched in a single step.

Direct Plan View FIB Liftout for Near-Surface Defect Analysis in TEM

2013 ◽  
Author(s):  
Max L. Lifson ◽  
Carla M. Chapman ◽  
D. Philip Pokrinchak ◽  
Phyllis J. Campbell ◽  
Greg S. Chrisman ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Silicon Germanium ◽  
Focused Ion Beam ◽  
Surface Defects ◽  
Ion Beam ◽  
Misfit Dislocations ◽  
Tem Analysis ◽  
Plan View ◽  
Near Surface ◽  
Straightforward Method

Abstract Plan view TEM imaging is a powerful technique for failure analysis and semiconductor process characterization. Sample preparation for near-surface defects requires additional care, as the surface of the sample needs to be protected to avoid unintentionally induced damage. This paper demonstrates a straightforward method to create plan view samples in a dual beam focused ion beam (FIB) for TEM studies of near-surface defects, such as misfit dislocations in heteroepitaxial growths. Results show that misfit dislocations are easily imaged in bright-field TEM and STEM for silicon-germanium epitaxial growth. Since FIB tools are ubiquitous in semiconductor failure analysis labs today, the plan view method presented provides a quick to implement, fast, consistent, and straightforward method of generating samples for TEM analysis. While this technique has been optimized for near-surface defects, it can be used with any application requiring plan view TEM analysis.

Fast Turn-around Failure Analysis of Metal Interconnection Using FIB and LA ICP-MS

2010 ◽  
Author(s):  
Zixiao Pan ◽  
Wei Wei ◽  
Fuhe Li
Keyword(s):  
Failure Analysis ◽  
Inductively Coupled Plasma ◽  
Structural Damage ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Detection Sensitivity ◽  
Chemical Contamination ◽  
Inductively Coupled ◽  
Minimal Sample ◽  
Icp Ms

Abstract This paper introduces our effort in failure analysis of a 200 nm thick metal interconnection on a glass substrate and covered with a passivation layer. Structural damage in localized areas of the metal interconnections was observed with the aid of focused ion beam (FIB) cross-sectioning. Laser ablation inductively coupled plasma mass spectroscopy (LA ICP-MS) was then applied to the problematic areas on the interconnection for chemical survey. LA ICP-MS showed direct evidence of localized chemical contamination, which has likely led to corrosion (or over-etching) of the metal interconnection and the assembly failure. Due to the high detection sensitivity of LA ICP-MS and its compatibility with insulating material analysis, minimal sample preparation is required. As a result, the combination of FIB and LA ICP-MS enabled successful meso-scale failure analysis with fast turnaround and reasonable cost.

Logical-to-Physical Device Navigation using Place-and-Route Data as an Alternative to LVS

2006 ◽  
Author(s):  
Roger Nicholson
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Traditional Methods ◽  
Navigation Data ◽  
Use Of Time ◽  
Place And Route ◽  
Physical Layout

Abstract Logical-to-physical device navigation for failure analysis is often used to drive physical probers and focused ion beam tools. Traditional methods of creating navigation data rely upon the use of time consuming Layout-versus-Schematic (LVS) based methods. By using existing place-and-route data, full cross-linked navigation between schematic and physical layout may be achieved in a fraction of the time that it takes for the LVS methods to be used. Place-and-route data offers significantly more information to the analyst than LVS based data.

BiCMOS Die Sort Yield Improvement from Isolation of a Localized Defect Mechanism and Precision TEM Cross Section

1997 ◽  
Author(s):  
J. Douglass ◽  
T. D. Myers ◽  
F. Tsai ◽  
R. Ketcheson ◽  
J. Errett
Keyword(s):  
Electron Microscopy ◽  
Cross Section ◽  
Focused Ion Beam ◽  
Yield Loss ◽  
Process Analysis ◽  
Ion Beam ◽  
Yield Improvement ◽  
Transmission Electron ◽  
Defect Mechanism ◽  
Water Residue

Abstract This paper describes how the authors used a combination of focused ion beam (FIB) microprobing, transmission electron microscopy (TEM), and data and process analysis to determine that localized water residue was causing a 6% yield loss at die sort.

Site-Specific Low Angle Plasma FIB Milling for Cross-Sectional Electrical Characterization

2019 ◽  
Author(s):  
Chuan Zhang ◽  
Jane Y. Li ◽  
John Aguada ◽  
Howard Marks
Keyword(s):  
Cross Section ◽  
Focused Ion Beam ◽  
Electrical Characteristic ◽  
Preparation Method ◽  
Ion Beam ◽  
Grazing Angle ◽  
Electrical Characterization ◽  
Sample Preparation Method ◽  
Cross Sectional ◽  
Site Specific

Abstract This paper introduces a novel sample preparation method using plasma focused ion-beam (pFIB) milling at low grazing angle. Efficient and high precision preparation of site-specific cross-sectional samples with minimal alternation of device parameters can be achieved with this method. It offers the capability of acquiring a range of electrical characteristic signals from specific sites on the cross-section of devices, including imaging of junctions, Fins in the FinFETs and electrical probing of interconnect metal traces.

Layout Overlay Techniques to Improve Failure Analysis

1998 ◽  
Author(s):  
Christian Burmer ◽  
Siegfried Görlich ◽  
Siegfried Pauthner
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
New Technologies ◽  
Ion Beam ◽  
Image Correlation ◽  
Microelectronic Devices ◽  
Overlay Technique ◽  
Correlation Techniques ◽  
Navigation Software ◽  
Image Format

Abstract New layout overlay technique has been developed based on standard image correlation techniques to support failure analysis in modern microelectronic devices, which are critical to analyze because they are realized in new technologies using sub-ìm design rules, chemical mechanical polishing techniques (CMP) and autorouted design techniques. As the new technique is realized as an extension of a standard CAD-navigation software and as it makes use of standard image format "TIFF" for data input, which is available at all modern equipments for failure analysis, these technique can be applied to all modern failure analysis methods. Here examples are given for three areas of application: circuit modification using Focused Ion Beam (FIB), support of preparation for backside inspection and fault localization using emission microscopy.

Solving the Voltage Contrast on Floating Substrate with Standard FA Toolset

2016 ◽  
Author(s):  
Julien Goxe ◽  
Béatrice Vanhuffel ◽  
Marie Castignolles ◽  
Thomas Zirilli
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Sample Preparation ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Silicon On Insulator ◽  
Mixed Signal ◽  
Voltage Contrast ◽  
Scanning Electron

Abstract Passive Voltage Contrast (PVC) in a Scanning Electron Microscope (SEM) or a Focused Ion Beam (FIB) is a key Failure Analysis (FA) technique to highlight a leaky gate. The introduction of Silicon On Insulator (SOI) substrate in our recent automotive analog mixed-signal technology highlighted a new challenge: the Bottom Oxide (BOX) layer, by isolating the Silicon Active Area from the bulk made PVC technique less effective in finding leaky MOSFET gates. A solution involving sample preparation performed with standard FA toolset is proposed to enhance PVC on SOI substrate.

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