Efficient Fault Isolation and Failure Analysis Methods to Root Cause Defects in Microprocessors

2019 ◽  
Author(s):  
Hasan Faraby ◽  
Tristan Deborde ◽  
Martin von Haartman
Keyword(s):  
Failure Analysis ◽  
Success Rate ◽  
State Of The Art ◽  
Fault Isolation ◽  
High Success Rate ◽  
Electrical Isolation ◽  
Root Cause ◽  
Isolation Techniques ◽  
Analysis Methods

Abstract This paper analyzes the through-put time and output of fault isolation and failure analysis (FI/FA) flows on state-of-the-art microprocessors. An average reduction in through-put time of 40% was demonstrated with a shortened FI/FA flow while still maintaining a high success rate. The direct FA/nano-probing flow which was utilized by up to around 90% of the fail cases omitted the optical fault isolation step and instead expanded the use of plasma FIB, nano-probing and electrical isolation techniques (such as diagnosis tools). The end result is shorter through-put time and higher FI/FA volume which is important in order to achieve a faster production ramp. In the paper two cases studies are presented to demonstrate the new efficient FI/FA techniques.

Single Device Characterization by Nano-probing to Identify Failure Root Cause

2005 ◽  
Author(s):  
Chao-Chi Wu ◽  
Jon C. Lee ◽  
Jung-Hsiang Chuang ◽  
Tsung-Te Li
Keyword(s):  
Failure Analysis ◽  
Success Rate ◽  
Failure Mechanism ◽  
Fault Isolation ◽  
Device Characterization ◽  
Nano Technology ◽  
Analysis Techniques ◽  
Root Cause ◽  
Visual Defects ◽  
Lower Success Rate

Abstract In general failure analysis cases, a less invasive fault isolation approach can be utilized to resolve a visual root cause defect. In the case of nano technology, visual defects are not readily resolved, due to an increase in non-visible defects. The nonvisible defects result in a lower success rate since conventional FA methods/tools are not efficient in identifying the failure root cause. For the advanced nanometer process, this phenomenon is becoming more common; therefore the utilization of advanced techniques are required to get more evidence to resolve the failure mechanism. The use of nanoprobe technology enables advanced device characterization h order to obtain more clues to the possible failure mechanism before utilizing the traditional physical failure analysis techniques.

ATPG Testing and Diagnosis Implementation in Failure Analysis for a Fast and Efficient Iterative ATPG Diagnosis and Fault Isolation

2017 ◽  
Author(s):  
Eric Barbian ◽  
Rommel Estores
Keyword(s):  
Failure Analysis ◽  
Dynamic Analysis ◽  
Creative Thinking ◽  
Complex Analysis ◽  
Cost Effective ◽  
Fault Isolation ◽  
Practical Implementation ◽  
Root Cause ◽  
Isolation Techniques ◽  
Thinking Process

Abstract This paper will present a practical implementation of ATPG testing and diagnosis in Failure Analysis resulting in a fast and efficient iterative ATPG diagnosis and fault isolation. On this implementation, a compact test HW instead of an ATE is used for cost-effective ATPG testing and characterization capability. The advantages of this implementation are combined with ATPG tools to make it possible to achieve a faster and more efficient implementation of iterative ATPG diagnosis, Dynamic Analysis by Laser Stimulation (DALS) analysis or similar techniques. The requirements needed in order to implement ATPG testing and diagnosis in FA lab will be discussed. Success in determining root cause, especially on the complex analysis cases is determined by the complimentary combination of various fault isolation techniques. Knowledge of the fundamentals of these techniques combined with creative thinking process of the analyst leads to the approaches and solutions that maximize the combined advantages of these techniques.

Failure Analysis From Back Side of Die

1996 ◽  
Author(s):  
N.M. Wu ◽  
K. Weaver ◽  
J.H. Lin
Keyword(s):  
Failure Analysis ◽  
Fault Isolation ◽  
Back Side ◽  
Induced Current ◽  
Front Side ◽  
Root Cause ◽  
Isolation Techniques ◽  
Cause Of Failure ◽  
Emission Microscopy ◽  
Side Emission

Abstract With increasing complexity of circuit layout on the die and special packages in which the die are flipped over, failure analysis on the die front side, sometimes, can not solve the problems or is not possible by opening the front side of the package to expose the die front side. This paper discusses fault isolation techniques and procedures used on the back side of the die. The two major back side techniques, back side emission microscopy and back side OBIC (Optical Beam Induced Current), are introduced and applied to solve real problems in failure analysis. A back side decapsulation technique and procedure are also introduced. Last, several examples are given. The results indicated that the success in finding root cause of failure is greatly increased when these techniques are used in addition to the traditional front side analysis approaches.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

SEM-Based Nanoprobing on 40, 32 and 28 nm CMOS Devices Challenges for Semiconductor Failure Analysis

2013 ◽  
Author(s):  
Erik Paul ◽  
Holger Herzog ◽  
Sören Jansen ◽  
Christian Hobert ◽  
Eckhard Langer
Keyword(s):  
Electron Microscope ◽  
High Resolution ◽  
Scanning Electron Microscope ◽  
Failure Analysis ◽  
Case Studies ◽  
State Of The Art ◽  
Root Cause ◽  
Highly Efficient ◽  
Technology Nodes ◽  
Scanning Electron

Abstract This paper presents an effective device-level failure analysis (FA) method which uses a high-resolution low-kV Scanning Electron Microscope (SEM) in combination with an integrated state-of-the-art nanomanipulator to locate and characterize single defects in failing CMOS devices. The presented case studies utilize several FA-techniques in combination with SEM-based nanoprobing for nanometer node technologies and demonstrate how these methods are used to investigate the root cause of IC device failures. The methodology represents a highly-efficient physical failure analysis flow for 28nm and larger technology nodes.

Advanced Scan Diagnosis Based Fault Isolation and Defect Identification for Yield Learning

2005 ◽  
Author(s):  
Chris Eddleman ◽  
Nagesh Tamarapalli ◽  
Wu-Tung Cheng
Keyword(s):  
Failure Analysis ◽  
Fault Location ◽  
Effective Means ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Yield Analysis ◽  
Isolation Techniques ◽  
Yield Learning ◽  
Time Required ◽  
Inspection Data

Abstract Yield analysis of sub-micron devices is an ever-increasing challenge. The difficulty is compounded by the lack of in-line inspection data as many companies adopt foundry or fab-less models for acquiring wafers. In this scenario, failure analysis is increasingly critical to help drive yields. Failure analysis is a process of fault isolation, or a method of isolating failures as precisely as possible followed by identification of a physical defect. As the number of transistors and metal layers increase, traditional fault isolation techniques are less successful at isolating a cause of failures. Costs are increasing due to the amount of time needed to locate the physical defect. One solution to the yield analysis problem is scan diagnosis based fault isolation. Previous scan diagnosis based techniques were limited with little information about the type of fault and confidence of diagnosis. With new scan diagnosis algorithms it is now possible to not only isolate, but to identify the type of fault as well as assigning a confidence ranking prior to any destructive analysis. This paper presents multiple case studies illustrating the application of scan diagnosis as an effective means to achieve yield enhancement. The advanced scan diagnostic tool used in this study provides information about the fault type as well as fault location. This information focuses failure analysis efforts toward a suspected defect, decreasing the cycle time required to determine root cause, as well as increasing the over all success rate.

Pseudo-Dynamic Fault Isolation Technique Using Backside Emission Microscopy – Case Study, Where All Other Methods Fail

2002 ◽  
Author(s):  
Yoav Weizman ◽  
Ezra Baruch ◽  
Michael Zimin
Keyword(s):  
Failure Analysis ◽  
Process Variations ◽  
Fault Isolation ◽  
Operating Conditions ◽  
Detection Sensitivity ◽  
Isolation Technique ◽  
Root Cause ◽  
Emission Microscopy ◽  
Failure Location ◽  
Noisy Background

Abstract Emission microscopy is usually implemented for static operating conditions of the DUT. Under dynamic operation it is nearly impossible to identify a failure out of the noisy background. In this paper we describe a simple technique that could be used in cases where the temporal location of the failure was identified however the physical location is not known or partially known. The technique was originally introduced to investigate IDDq failures (1) in order to investigate timing related issues with automated tester equipment. Ishii et al (2) improved the technique and coupled an emission microscope to the tester for functional failure analysis of DRAMs and logic LSIs. Using consecutive step-by-step tester halting coupled to a sensitive emission microscope, one is able detect the failure while it occurs. We will describe a failure analysis case in which marginal design and process variations combined to create contention at certain logic states. Since the failure occurred arbitrarily, the use of the traditional LVP, that requires a stable failure, misled the analysts. Furthermore, even if we used advanced tools as PICA, which was actually designed to locate such failures, we believe that there would have been little chance of observing the failure since the failure appeared only below 1.3V where the PICA tool has diminished photon detection sensitivity. For this case the step-by-step halting technique helped to isolate the failure location after a short round of measurements. With the use of logic simulations, the root cause of the failure was clear once the failing gate was known.

Application of Focused Ion Beam System as A Defect Localization and Root Cause Analysis Tool

2001 ◽  
Author(s):  
C.C. Ooi ◽  
K.H. Siek ◽  
K.S. Sim
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Fault Isolation ◽  
Analysis Tool ◽  
Root Cause ◽  
Beam System ◽  
Defect Localization ◽  
Challenging Environment ◽  
Microprocessor Technology

Abstract Focused ion beam system has been widely used as a critical failure analysis tool as microprocessor technology advances at a ramping speed. It has become an essential step in failure analysis to reveal physical defects post electrical fault isolation. In this highly competitive and challenging environment prevalent today, failure analysis throughput time is of utmost important. Therefore quick, efficient and reliable physical failure analysis technique is needed to avoid potential issues from becoming bigger. This paper will discuss the applications of FIB as a defect localization and root cause determination tool through the passive charge contrast technique and pattern FIB analysis.

Challenges of System Level Failure Analysis of Electronics in the Automotive Industry

2017 ◽  
Author(s):  
Bence Hevesi
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Automotive Industry ◽  
Root Cause Analysis ◽  
Fault Isolation ◽  
System Level ◽  
Cause Analysis ◽  
Root Cause ◽  
Analysis Workflow

Abstract In this paper, different failure analysis (FA) workflows are showed which combines different FA approaches for fast and efficient fault isolation and root cause analysis in system level products. Two case studies will be presented to show the importance of a well-adjusted failure analysis workflow.

Failure Analysis Work Flow for Electrical Shorts in Triple Stacked 3D TSV Daisy Chains

2015 ◽  
Vol 2015 (1) ◽  
pp. 000469-000473 ◽  
Author(s):  
J. Gaudestad ◽  
A. Orozco ◽  
I. De Wolf ◽  
T. Wang ◽  
T. Webers ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Fault Isolation ◽  
Root Cause ◽  
Current Path ◽  
Dual Beam ◽  
Resolution Imaging ◽  
Magnetic Field Imaging ◽  
Non Destructive

In this paper we show an efficient workflow that combines Magnetic Field Imaging (MFI) and Dual Beam Plasma Focused Ion Beam (DB-PFIB) for fast and efficient Fault Isolation and root cause analysis in 2.5/3D devices. The work proves MFI is the best method for Electric Fault Isolation (EFI) of short failures in 2.5/3D Through Silicon Via (TSV) triple stacked devices in a true non-destructive way by imaging the current path. To confirm the failing locations and to do Physical Failure Analysis (PFA), a DB-PFIB system was used for cross sectioning and volume analysis of the TSV structures and high resolution imaging of the identified defects. With a DB-PFIB, the fault is exposed and analyzed without any sample prep artifacts seen in mechanical polishing or laser preparation techniques and done in a considerably shorter amount of time than that required when using a traditional Gallium Focused Ion Beam (FIB).

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