The advancement of silicon-on-insulator (SOI) devices and their basic properties

2020 ◽  
Vol 23 (3) ◽  
pp. 227-252
Author(s):  
T.E. Rudenko ◽  
◽  
A.N. Nazarov ◽  
V.S. Lysenko ◽  
◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Basic Properties ◽  
Soi Devices

Application of FIB Circuit Edit in Analysis of Memory Failure of SOI Devices

2006 ◽  
Author(s):  
Z. G. Song ◽  
S. K. Loh ◽  
X. H. Zheng ◽  
S.P. Neo ◽  
C. K. Oh
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Silicon On Insulator ◽  
First Case ◽  
Edx Analyses ◽  
Memory Failure ◽  
Soi Devices ◽  
Voltage Contrast ◽  
Soi Technology

Abstract This article presents two cases to demonstrate the application of focused ion beam (FIB) circuit edit in analysis of memory failure of silicon on insulator (SOI) devices using XTEM and EDX analyses. The first case was a single bit failure of SRAM units manufactured with 90 nm technology in SOI wafer. The second case was the whole column failure with a single bit pass for a SRAM unit. From the results, it was concluded that FIB circuit edit and electrical characterization is a good methodology for further narrowing down the defective location of memory failure, especially for SOI technology, where contact-level passive voltage contrast is not suitable.

High Temperature Endurance of Packaged SOI Devices for Signal Conditioning and Processing Applications

2011 ◽  
Vol 2011 (HITEN) ◽  
pp. 000251-000254
Author(s):  
S T Riches ◽  
C Johnston ◽  
M Sousa ◽  
P Grant
Keyword(s):  
High Temperature ◽  
Electronic Materials ◽  
Silicon On Insulator ◽  
Electrical Performance ◽  
Research Centre ◽  
Signal Conditioning ◽  
Reliability Data ◽  
Die Attach ◽  
Soi Devices ◽  
Formed Part

Silicon on Insulator (SOI) device technology is fulfilling a niche requirement for electronics that functions satisfactorily at operating temperatures of >200°C. Most of the reliability data on the high temperature endurance of the devices is generated on the device itself with little attention being paid to the packaging technology around the device. Similarly, most of the reliability data generated on high temperature packaging technologies uses testpieces rather than real devices, which restricts any conclusions on long term electrical performance. This paper presents results of high temperature endurance studies on SOI devices combined with high temperature packaging technologies relevant to signal conditioning and processing functions for sensors in down-well and aero-engine applications. The endurance studies have been carried out for up to 7,056 hours at 250°C, with functioning devices being tested periodically at room temperature, 125°C and 250°C. Different die attach and wire bond options have been included in the study and the performance of multiplexers, transistors, bandgap voltage, oscillators and voltage regulators functional blocks have been characterised. This work formed part of the UPTEMP project which was set-up with support from UK Technology Strategy Board and the EPSRC. The project brought together a consortium of end-users (Sondex Wireline and Vibro-Meter UK), electronic module manufacturers (GE Aviation Systems Newmarket) and material suppliers (Gwent Electronic Materials and Thermastrate Ltd) with Oxford University-Materials Department, the leading UK high temperature electronics research centre.

Novel and Practical Method of Through Silicon FIB Editing of SOI Devices

2005 ◽  
Author(s):  
R.K. Jain ◽  
T.R. Lundquist ◽  
M.E. Antolik ◽  
M.A. Thompson
Keyword(s):  
Etch Rate ◽  
Ion Beam ◽  
Practical Method ◽  
Silicon On Insulator ◽  
Beam Deflection ◽  
Future Technology ◽  
Placement Accuracy ◽  
Soi Devices ◽  
Beam Currents ◽  
Complete Process

Abstract Circuit edit techniques have been developed for silicon-on-insulator (SOI) devices using a coaxial photon-ion column. Novel trenching, navigation and milling methods, utilizing sub pico-Amp beam currents provide enhanced capability for editing devices with decreased geometries including buried (Box) thickness. Flat trenches 200x200µm were obtained using real time optical fringe monitoring with 125nm accuracy with 950nm λ and FIB bit map milling to adjust for parallelism to the ILD0. This bit map milling technique controlled the etch rate to maintain trench flatness by correlating the optical fringes to the bit map grayscales to vary the dwell time of the ion beam across the trench floor. Through highly accurate, CAD directed beam deflection control, beam placement accuracy in the sub 20nm regime can readily be accomplished, sub pA beam currents provide ultracontrolled etch rates and high aspect ratio (HAR) capability. Complete process definitions, techniques and results are reported. These techniques have proven successful in circuit edit below 90nm, and are expected to meet future technology circuit edit requirements down to 45nm.

Effectiveness of Barrier Layer Metallizations in Long Term High Temperature Endurance Tests on Wire Bond Interconnections

2013 ◽  
Vol 10 (4) ◽  
pp. 163-170
Author(s):  
S. T. Riches ◽  
C. Johnston ◽  
A. Lui
Keyword(s):  
High Temperature ◽  
Barrier Layer ◽  
Failure Modes ◽  
Critical Factor ◽  
Silicon On Insulator ◽  
Wire Bond ◽  
Soi Devices ◽  
Operating Temperatures ◽  
Temperature Storage

Silicon on insulator (SOI) device technology has been shown to be capable of functioning satisfactorily at operating temperatures of >200°C, with device lifetimes of 5 y at 225°C being declared. One of the key areas governing the lifetime of the packaged electronic devices is the reliability of the wire bond interconnection between the device and the package or substrate connection. Extended temperature storage testing at 250°C of packaged SOI devices has highlighted end of life failure modes associated with wire bond connections. SOI devices are normally supplied with an aluminum based bond pad metallization, which are not suitable for direct connection of Au wire at operating temperatures of >125°C, due to the formation of Au-Al intermetallics. It is possible to postprocess silicon wafers to deposit barrier and connection materials to create a monometallic Au-Au joint at the surface. For long term endurance at temperatures >200°C, the effectiveness of the barrier layer in preventing diffusion of the aluminum bond pad metallization to interact with the Au is a critical factor. This paper presents results of studies carried out on two postprocess metallization systems Au/TiW and Au/Pd/Ni deposited onto aluminum bond pads, which have been Au wire bonded and exposed to 250°C temperature storage for up to 13,000 h. The results have shown that the barrier layers are not effective in preventing diffusion of the aluminum bond pad metallization to create Au-Al based intermetallics. The results are compared with Al-1%Si wire bonding to the aluminum bond pad, where the second wedge bond is attached to a Au/Ni plated metallization, where the degradation appears to be less severe. Recommendations for designing stable wire bond interconnection systems for extended high temperature operation will be presented.

MONTE-CARLO SIMULATION OF ULTRA-THIN FILM SILICON-ON-INSULATOR MOSFETs

2013 ◽  
Vol 22 (01) ◽  
pp. 1350001
Author(s):  
FRANCISCO GÁMIZ ◽  
CARLOS SAMPEDRO ◽  
LUCA DONETTI ◽  
ANDRES GODOY
Keyword(s):  
Monte Carlo ◽  
Ground Plane ◽  
Silicon On Insulator ◽  
Slab Thickness ◽  
Short Channel ◽  
Fully Depleted ◽  
Ensemble Monte Carlo ◽  
Soi Devices ◽  
Monte Carlo Simulator ◽  
The Impact

State-of-the-Art devices are approaching to the performance limit of traditional MOSFET as the critical dimensions are shrunk. Ultrathin fully depleted Silicon-on-Insulator transistors and multi-gate devices based on SOI technology are the best candidates to become a standard solution to overcome the problems arising from such aggressive scaling. Moreover, the flexibility of SOI wafers and processes allows the use of different channel materials, substrate orientations and layer thicknesses to enhance the performance of CMOS circuits. From the point of view of simulation, these devices pose a significant challenge. Simulations tools have to include quantum effects in the whole structure to correctly describe the behavior of these devices. The Multi-Subband Monte Carlo (MSB-MC) approach constitutes today's most accurate method for the study of nanodevices with important applications to SOI devices. After reviewing the main basis of MSB-MC method, we have applied it to answer important questions which remain open regarding ultimate SOI devices. In the first part of the chapter we present a thorough study of the impact of different Buried OXide (BOX) configurations on the scaling of extremely thin fully depleted SOI devices using a Multi-Subband Ensemble Monte Carlo simulator (MS-EMC). Standard thick BOX, ultra thin BOX (UTBOX) and UTBOX with ground plane (UTBOX+GP) solutions have been considered in order to check their influence on short channel effects (SCEs). The simulations show that the main limiting factor for downscaling is the DIBL and the UTBOX+GP configuration is the only valid one to downscale SGSOI transistors beyond 20 nm channel length keeping the silicon slab thickness above the theoretical limit of 5 nm, where thickness variability and mobility reduction would play an important role. In the second part, we have used the multisubband Ensemble Monte Carlo simulator to study the electron transport in ultrashort DGSOI devices with different confinement and transport directions. Our simulation results show that transport effective mass, and subband redistribution are the main factors that affect drift and scattering processes and, therefore, the general performance of DGSOI devices when orientation is changed

Failure Analysis of SOI Bipolar Device Using Photon Emission Microscopy

2004 ◽  
Author(s):  
Todd M. Simons ◽  
Bob Davis
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Photon Emission ◽  
Silicon On Insulator ◽  
The Other ◽  
No Emission ◽  
Analysis Process ◽  
Soi Devices ◽  
Emission Microscopy ◽  
Optical Paths

Abstract Photon emission microscopy (PEM) provides a valuable first step in the failure analysis process. An analysis of a mixed signal bipolar/CMOS silicon on insulator (SOI) device revealed an abnormal emission site that appeared to emanate from the oxide isolation ring. Subsequent mechanical probing of the emitting bipolar transistor revealed node voltages nearly identical to a known good reference unit that had no emission site at the affected transistor. This article analyzes the reasons for the emission site on one transistor and not the other even though the node voltages were the same. It was observed that while the node voltages were nearly identical, the available current paths were not. The different paths directly related to the amount of available carriers for recombination in the base. The construction of the SOI device creates unique optical paths for emission sites not observed in non-SOI devices. It can be concluded that the failure mechanism does not always reside at the abnormal PEM site.

A Path to Energy Efficiency and Reliability for ICs: Fully Depleted Silicon-on-Insulator (FD-SOI) Devices Offer Many Advantages

2018 ◽  
Vol 10 (4) ◽  
pp. 24-33 ◽  
Author(s):  
Bich-Yen Nguyen ◽  
Philippe Flatresse ◽  
Jamie Schaeffer ◽  
Franck Arnaud ◽  
Souhir Mhira ◽  
...  
Keyword(s):  
Energy Efficiency ◽  
Silicon On Insulator ◽  
Fully Depleted ◽  
Soi Devices ◽  
Efficiency And Reliability

Defect Localization Using Time-Resolved Photon Emission on SOI Devices that Fail Scan Tests

2002 ◽  
Author(s):  
Dan Bodoh ◽  
Ed Black ◽  
Kris Dickson ◽  
Ron Wang ◽  
Tim Cheng ◽  
...  
Keyword(s):  
Case Studies ◽  
Flip Chip ◽  
Near Infrared ◽  
Photon Emission ◽  
Silicon On Insulator ◽  
Time Resolved ◽  
Defect Localization ◽  
Emission System ◽  
Soi Devices ◽  
Practice Time

Abstract Time-resolved photon emission has been shown to be useful in analyzing clock skews and timing-related defects in flip-chip devices. In practice, time-resolved photon emission using the S-25 Quantar detector cannot be used at long loop lengths (typically >10 μs). This paper discusses a near-infrared (NIR) optimized time-resolved emission system to demonstrate that even with long loop lengths time-resolved photon emission can be extremely useful for defect localization. Specifically, it describes time-resolved photon emission system, and shows how time-resolved photon emission was used to solve two different issues that caused scan fails on silicon-on-insulator devices, and briefly discusses the interpretation of optical waveforms. The two issues are presented as case studies.

Floating Substrate Passive Voltage Contrast (FSPVC)

2006 ◽  
Author(s):  
Mark W. Jenkins ◽  
Paiboon Tangyunyong ◽  
Edward I. Cole ◽  
Jerry M. Soden ◽  
Jeremy A. Walraven ◽  
...  
Keyword(s):  
Electron Emission ◽  
Light Emission ◽  
Secondary Electron Emission ◽  
Gate Oxide ◽  
Silicon On Insulator ◽  
Bulk Silicon ◽  
The Past ◽  
Soi Devices ◽  
Gate Oxide Short ◽  
Voltage Contrast

Abstract Light emission [1,2] and passive voltage contrast (PVC) [3,4] are common failure analysis tools that can quickly identify and localize gate oxide short sites. In the past, PVC was not used on electrically floating substrates or SOI (silicon-on-insulator) devices due to the conductive path needed to “bleed off” charge. In PVC, the SEM’s primary beam induces different equilibrium potentials on floating versus grounded (0 V) conductors, thus generating different secondary electron emission intensities for fault localization. Recently we obtained PVC signals on bulk silicon floating substrates and SOI devices. In this paper, we present details on identifying and validating gate shorts utilizing this Floating Substrate PVC (FSPVC) method.

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