Techniques for Identification of Silver Migration in Plastic Encapsulated Devices Assembled with Molding Compound Containing Red Phosphorus Flame Retardant Material

Author(s):  
Ronald R. Hylton

Abstract This paper describes the electrical signatures and failure analysis techniques used to identify plastic encapsulated devices that have failed due to silver migration. This migration, which produces resistive leakages between adjacent pins, has been associated with molding compounds that utilize red phosphorous as a flame retardant material. A description of the failure mechanism is also presented.

Author(s):  
Y.E. Hong ◽  
M.T.T. We

Abstract As transistor dimension shrinks down below submicron to cater for higher speed and higher packing density, it is very important to characterize the shrinkage carefully to avoid unwanted parametric problems. Leakage current across short poly end-cap is a new failure mechanism that falls in this category and was for the first time, uncovered in submicron multilayered CMOS devices. This mechanism was responsible for a systematic yield problem; identified as the 'centre wafer striping' functional failure problem. This paper presents the advanced failure analysis techniques and defect modeling used to narrow down and identify this new mechanism. Post process change by loosening the marginal poly end-cap criteria eliminated the problem completely.


Author(s):  
E. H. Yeoh ◽  
W. M. Mak ◽  
H. C. Lock ◽  
S. K. Sim ◽  
C. C. Ooi ◽  
...  

Abstract As device interconnect layers increase and transistor critical dimensions decrease below sub-micron to cater for higher speed and higher packing density, various new and subtle failure mechanisms have emerged and are becoming increasingly prevalent. Silicon dislocation is a new failure mechanism that falls in this category and was for the first time, uncovered in submicron multilayered CMOS devices. This mechanism was responsible for a systematic yield problem; identified as the 'centre GFA wafer' functional failure problem. In this paper, several breakthrough failure analysis techniques used to narrow down and identify this new mechanism will be presented. Root cause determination and potential solution to this problem will also be discussed.


Author(s):  
Rafael Huerta ◽  
Nevil Wu

Abstract Red phosphorous is one of the inorganic phosphorous compounds used as a flame retardant in microelectronic applications. One of the concerns is a red phosphorus induced pin-to-pin short in the molding compound. This paper discusses the red phosphorous-induced shorts in a 100 Lead TQFP (14x20x1.4mm) plastic package. The devices first failed on boards in the field. After de-soldering them from the boards, the devices were tested and found to have resistive pin-to-pin shorts. Common failure analysis techniques, including parallel lapping, cross sectioning, and X-ray, failed to reveal the resistive shorts and the shorting mechanism. Removing the molding compound by means of a wet chemical etching method using sulfuric acid on a hot plate worked very well and enabled to expose particles in three dimensions. It was concluded that the resistive shorts were not necessarily due to a single large phosphorous particle, but due to small and fragmented pieces of phosphorous.


Author(s):  
Hei-Ruey Harry Jen ◽  
Gerald S. D’Urso ◽  
Harold Andrews

Abstract When a failure analysis (FA) involves a multiple layer structure separated by a polymeric material such as Benzocyclobutene (BCB), in a plastic package, it becomes a very challenging task to find out where the failure site is and how it failed. This is due to the fact that the chemical de-processing procedure removes BCB as well as the plastic molding compound. This paper outlines the studies carried out to determine the failure site and the root cause of the failure mechanism in a multilayer circuit and the steps taken to fix the problems. The methodology and results of this study are applicable to many other types of circuits.


Author(s):  
P.K. Tan ◽  
Z.H. Mai ◽  
S.L. Toh ◽  
E. Hendarto ◽  
Q. Deng ◽  
...  

Abstract With the scaling down of semiconductor devices to nanometer range, physical failure analysis (PFA) has become more challenging. In this paper, a different method of performing PFA to identify a physical vertical short of intermetal layer in nanoscale devices is discussed. The proposed chemical etch and backside chemical etch PFA techniques have the advantages of sample preparation evenness and efficiency compared to conventional PFA. This technique also offers a better understanding of the failure mechanism and is easier to execute in identifying the vertical short issue.


Author(s):  
Chao-Chi Wu ◽  
Jon C. Lee ◽  
Jung-Hsiang Chuang ◽  
Tsung-Te Li

Abstract In general failure analysis cases, a less invasive fault isolation approach can be utilized to resolve a visual root cause defect. In the case of nano technology, visual defects are not readily resolved, due to an increase in non-visible defects. The nonvisible defects result in a lower success rate since conventional FA methods/tools are not efficient in identifying the failure root cause. For the advanced nanometer process, this phenomenon is becoming more common; therefore the utilization of advanced techniques are required to get more evidence to resolve the failure mechanism. The use of nanoprobe technology enables advanced device characterization h order to obtain more clues to the possible failure mechanism before utilizing the traditional physical failure analysis techniques.


Author(s):  
Martin J. McVeigh

Abstract A case history is presented for the failure analysis of a 0.5u CMOS A/D converter in which high fallout occurred after autoclave stressing. The observed failure mode of degraded signal-to-noise distortion (SINAD) ratio (measured in dB) was found to affect devices within a specific bandwidth centered around 5MHz. From a circuit designer’s viewpoint, an explanation for this unique failure mode did not readily present itself. Yet, using straightforward failure analysis techniques, involving laser ablation of photoresist and selective etching of passivation, the specific failing circuit block was isolated. Crosssectional analysis, scanning electron microscopy (SEM), and energy dispersive spectroscopy (EDS) found evidence of residual photoresist at topography related voids in the nitride passivation layer. The photoresist reacts with moisture in the autoclave, resulting in increased capacitance at minimum-spaced top layer metal lines. This failure mechanism correlates with the observed maximum SINAD degradation around 5MHz: at this frequency the signals along the affected metal lines are at their maximum voltage swing. This failure mechanism is potentially an issue for any similar high-speed, high-resolution designs.


RSC Advances ◽  
2019 ◽  
Vol 9 (43) ◽  
pp. 24935-24941 ◽  
Author(s):  
Zhi Chen ◽  
Jianxin Du ◽  
Xiangmei Li ◽  
Zhili Xie ◽  
Yan Wang ◽  
...  

The failure mechanism of red phosphorus retardant PA66 electrical connectors is investigated.


Author(s):  
Amy Poe ◽  
Steve Brockett ◽  
Tony Rubalcava

Abstract The intent of this work is to demonstrate the importance of charged device model (CDM) ESD testing and characterization by presenting a case study of a situation in which CDM testing proved invaluable in establishing the reliability of a GaAs radio frequency integrated circuit (RFIC). The problem originated when a sample of passing devices was retested to the final production test. Nine of the 200 sampled devices failed the retest, thus placing the reliability of all of the devices in question. The subsequent failure analysis indicated that the devices failed due to a short on one of two capacitors, bringing into question the reliability of the dielectric. Previous ESD characterization of the part had shown that a certain resistor was likely to fail at thresholds well below the level at which any capacitors were damaged. This paper will discuss the failure analysis techniques which were used and the testing performed to verify the failures were actually due to ESD, and not caused by weak capacitors.


Author(s):  
Kuo Hsiung Chen ◽  
Wen Sheng Wu ◽  
Yu Hsiang Shu ◽  
Jian Chan Lin

Abstract IR-OBIRCH (Infrared Ray – Optical Beam Induced Resistance Change) is one of the main failure analysis techniques [1] [2] [3] [4]. It is a useful tool to do fault localization on leakage failure cases such as poor Via or contact connection, FEoL or BEoL pattern bridge, and etc. But the real failure sites associated with the above failure mechanisms are not always found at the OBIRCH spot locations. Sometimes the real failure site is far away from the OBIRCH spot and it will result in inconclusive PFA Analysis. Finding the real failure site is what matters the most for fault localization detection. In this paper, we will introduce one case using deep sub-micron process generation which suffers serious high Isb current at wafer donut region. In this case study a BEoL Via poor connection is found far away from the OBIRCH spots. This implies that layout tracing skill and relation investigation among OBIRCH spots are needed for successful failure analysis.


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