Electrical Signature Verification of a Lightly Doped Drain Profile Abnormality in a 65nm Device via Nano-Probing and Junction Stain TEM

2009 ◽  
Author(s):  
Jie Su ◽  
Sanan Liang ◽  
Yoyo Wen ◽  
May Yang ◽  
Linfeng Wu ◽  
...  
Keyword(s):  
Failure Mechanism ◽  
Memory Function ◽  
Random Access ◽  
Signature Verification ◽  
Physical Analysis ◽  
Electronic Microscopy ◽  
Access Memory ◽  
Tem Analysis ◽  
Root Cause ◽  
Lightly Doped Drain

Abstract Failures caused by threshold voltage (Vt) shifts in sub-100nm technology transistors have become very difficult to both analyze and determine the failure mechanism. The failure mechanisms for Vt shifts are typically non-visible for traditional physical analysis methods such as SEM inspection or traditional TEM analysis. This paper demonstrates how nano-probing was used to carefully and fully characterize the Vt shift failure to determine a specific electrical signature for a specific failure mechanism and then with junction stain Transmission Electronic Microscopy (TEM) verify the subtle doping defect affecting the Static Random Access Memory function in the 65nm generation node. Device failure due to a lack of Lightly Dope Drain (LDD) implant induced by an inconspicuous spacer defect was determined to be the root cause of the failure.

Characterization of Gate Oxide Pinhole Defect in NMOS FinFET Devices

2017 ◽  
Author(s):  
Liangshan Chen ◽  
Arnaud Bousquet ◽  
Tanya Schaeffer ◽  
Lucile C. Teague Sheridan ◽  
Lowell Hodgkins ◽  
...  
Keyword(s):  
Failure Mechanism ◽  
Electron Tomography ◽  
Gate Oxide ◽  
The Other ◽  
Physical Analysis ◽  
Tem Analysis ◽  
Root Cause ◽  
The Common ◽  
Tomography Analysis

Abstract This paper highlights the application of nanoprobing technique and electron tomography analysis to characterize the tiny gate oxide pinhole defect in NMOS FinFET devices. Nanoprobing technique was utilized to achieve a better understanding on the failure mechanism by characterizing the device electrical behaviors, and electron tomography, capable of mitigating the common projection issue encountered by general TEM analysis, was applied for physical analysis. It has been demonstrated through two cases, one logic fail and the other memory fail, that these two techniques together can effectively identify the root cause of pinhole defect. This type of pinhole defect, characterized by a tiny spot of oxide discontinuity and without excessive materials inter-diffusion, has been extremely challenging in FA analysis. This paper will provide the analysis details leading to the successful characterization of such type of oxide pinhole defect.

Identifying the Root Cause of Source-Drain Leakage Caused Soft Fail in Advanced Bulk FinFET Devices

2018 ◽  
Author(s):  
Liangshan Chen ◽  
Yuting Wei ◽  
Tanya Schaeffer ◽  
Chongkhiam Oh
Keyword(s):  
Careful Analysis ◽  
Physical Analysis ◽  
Device Structure ◽  
Tem Analysis ◽  
Root Cause ◽  
3D Architecture ◽  
Cause Of Failure ◽  
Electrical Analysis ◽  
Electrical Data

Abstract The paper reports the investigation on the root cause of source-drain leakage in bulk FinFET devices. While the failing device was readily isolated by nanoprobing technique and the electrical analysis pinpointed the potential defect location inside the Fin channel, the identification of physical root cause went through extreme challenges imposed by the tiny-sized device and the unique FinFET 3D architecture. The initial TEM analysis was misled by the projection of a species in the lamella surface and thus could not explain the electrical data. Careful analysis on the device structure was able to identify the origin of the species and led to the discovery of the actual root cause. This paper will provide the analysis details leading to the findings, and highlight the role of electrical understanding in not only providing guidance for physical analysis but also revealing the true root cause of failure in FinFET devices.

A New Approach for Screening Retention Time Failure Bits in DRAM Device

2013 ◽  
Author(s):  
Bonggu Sung ◽  
Daejung Kim ◽  
Yongjik Park ◽  
Joo-Sun Choi
Keyword(s):  
Retention Time ◽  
Random Access ◽  
Random Access Memory ◽  
Cell Plate ◽  
Dynamic Random Access Memory ◽  
Access Memory ◽  
New Approach ◽  
Root Cause ◽  
Storage Node ◽  
Node Voltage

Abstract In this paper, we investigate that Gate-Induced Drain Leakage (GIDL)-weak cells can be screened effectively by modulation of cell-plate voltage (VPlate) during retention time in dynamic random access memory (DRAM) with Negative Wordline bias scheme (NWL). Boosting storage-node voltage (VSP) by increase of VPlate is the root cause of generating additional GIDL fail bits.

Identification of a Non-LDD Induced Vt Shift Failure Mechanism via Nano-Probe Characterization

2010 ◽  
Author(s):  
Randal Mulder ◽  
Yuk Tsang
Keyword(s):  
Failure Mechanism ◽  
Threshold Voltage ◽  
Failure Mechanisms ◽  
Physical Analysis ◽  
Drive Current ◽  
Poly Silicon ◽  
Probe Analysis ◽  
Lightly Doped Drain ◽  
The Relationship

Abstract The relationship between blocked or depleted lightly doped drain (LDD) implants and threshold voltage (Vt) shifts resulting in suppressed drive current has been thoroughly investigated and characterized through nano-probe analysis. In this paper, a review for a technique for characterizing Vt shift failures is presented as well as a brief review of the LDD Vt shift failure. A case study is also presented showing the characterization, identification, and the physical analysis results for the symmetrical Vt shift failure mechanism. The method presented allows the analyst to differentiate between a Vt shift failure caused by a depleted LDD implant mechanism and a failure caused by dopant depletion in the gate poly-silicon. The results demonstrate that there are now at least two failure mechanisms that can be responsible for threshold voltage failures and it is likely that there are more that have yet to be discovered.

Analytically and empirically consistent characterization of resistive switching mechanism in Ag conducting-bridge random-access memory through pseudo-liquid approach

2021 ◽  
Author(s):  
Yeon-Joon Choi ◽  
Suhyun Bang ◽  
Tae-Hyeon Kim ◽  
Kyungho Hong ◽  
Sungjoon Kim ◽  
...  
Keyword(s):  
Resistive Switching ◽  
Random Access ◽  
Random Access Memory ◽  
Physical Analysis ◽  
Filament Formation ◽  
Access Memory ◽  
Metal Bonding ◽  
Conducting Bridge ◽  
Resistive Switching Mechanism

A new physical analysis of the filament formation in Ag conducting-bridge random-access memory (CBRAM) in consideration of the existence of inter-atomic attractions caused by metal bonding is suggested. The movement...

scholarly journals Resolution of Customer Return Non-Volatile Memory Data Retention Bit Failures through Bit Map Verification and Bit Cell Characterization by Nanoprobe Analysis

2021 ◽  
Author(s):  
Randal Mulder
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Nonvolatile Memory ◽  
Physical Analysis ◽  
Data Retention ◽  
Tem Analysis ◽  
Cell Characterization ◽  
Atomic Force ◽  
Programming Error ◽  
Non Volatile Memory

Abstract A major customer had been returning devices for nonvolatile memory (NVM) data retention bit failures. The ppm level was low but the continued fallout at the customer location was causing a quality and reliability concern. The customer wanted a resolution as to the cause of the failures and for a corrective action. An NVM bit data retention failure occurs when a programmed bit loses it programmed data state over time and flips to the opposite data state (0 -> 1 or 1 -> 0) causing a programming error. Previous failure analysis results on several failing devices with a single NVM bit data retention failure was inconclusive. TEM analysis showed no difference between the failing bit and neighboring passing bit. The lack of results led to the questioning of the accuracy of the bit map documentation and if the TEM analysis was being performed at the correct bit location. Bit map documentation takes the failing bit's electrical address and converts it to a physical address location. If the bit map documentation is incorrect, locating the failing bit is not possible and physical failure analysis will not be performed at the correct bit location. This paper will demonstrate how Atomic Force Probe (AFP) nanoprobe analysis was used to first verify the bit map documentation by determining the programming of bits at specific locations through bit cell characterization; and then characterize the failing bit location to verify the programming error and determine the possible failure mechanism based on its electrical signature followed by the appropriate physical analysis to determine the failure mechanism.

Nanoprobe Characterization of Soft SRAM bit Fails in Advanced Technologies

2019 ◽  
Author(s):  
Satish Kodali ◽  
Chen Zhe ◽  
Chong Khiam Oh
Keyword(s):  
Yield Loss ◽  
Performance Metrics ◽  
Root Cause ◽  
Advanced Technologies ◽  
Capacitance Voltage ◽  
Defect Localization ◽  
Cv Measurements ◽  
Lightly Doped Drain ◽  
Dc Characterization

Abstract Nanoprobing is one of the key characterization techniques for soft defect localization in SRAM. DC transistor performance metrics could be used to identify the root cause of the fail mode. One such case report where nanoprobing was applied to a wafer impacted by significant SRAM yield loss is presented in this paper where standard FIB cross-section on hard fail sites and top down delayered inspection did not reveal any obvious defects. The authors performed nanoprobing DC characterization measurements followed by capacitance-voltage (CV) measurements. Two probe CV measurement was then performed between the gate and drain of the device with source and bulk floating. The authors identified valuable process marginality at the gate to lightly doped drain overlap region. Physical characterization on an inline split wafer identified residual deposits on the BL contacts potentially blocking the implant. Enhanced cleans for resist removal was implemented as a fix for the fail mode.

Marginal RF Gain Investigation and Root Cause Determination

2013 ◽  
Author(s):  
Keith Harber ◽  
Steve Brockett
Keyword(s):  
Radio Frequency ◽  
Failure Analysis ◽  
Power Amplifier ◽  
Physical Analysis ◽  
Root Cause ◽  
S Parameter ◽  
Mode Of Operation ◽  
S Parameters

Abstract This paper outlines the failure analysis of a Radio Frequency only (RF-only) failure on a complex Multimode Multiband Power Amplifier (MMPA) module, where slightly lower gain was observed in one mode of operation. 2 port S-parameter information was collected and utilized to help localize the circuitry causing the issue. A slight DC electrical difference was observed, and simulation was utilized to confirm that difference was causing the observed S-parameters. Physical analysis uncovered a very visible cause for the RF-only failure.

Analysis of Leakage Failures in Flash Memory Devices and Root Cause Identification

2000 ◽  
Author(s):  
J. N. C. de Luna ◽  
M. O. del Fierro ◽  
J. L. Muñoz
Keyword(s):  
Flash Memory ◽  
Electromagnetic Interference ◽  
Yield Loss ◽  
High Amplitude ◽  
Physical Analysis ◽  
Input Buffer ◽  
Automated Test Equipment ◽  
Root Cause ◽  
Root Cause Identification ◽  
Test Process

Abstract An advanced flash bootblock device was exceeding current leakage specifications on certain pins. Physical analysis showed pinholes on the gate oxide of the n-channel transistor at the input buffer circuit of the affected pins. The fallout contributed ~1% to factory yield loss and was suspected to be caused by electrostatic discharge or ESD somewhere in the assembly and test process. Root cause investigation narrowed down the source to a charged core picker inside the automated test equipment handlers. By using an electromagnetic interference (EMI) locator, we were able to observe in real-time the high amplitude electromagnetic pulse created by this ESD event. Installing air ionizers inside the testers solved the problem.

Analysis of FSRAM Single Bit Failures Due to Unique Dislocations

1998 ◽  
Author(s):  
Phil Schani ◽  
S. Subramanian ◽  
Vince Soorholtz ◽  
Pat Liston ◽  
Jamey Moss ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Temperature Sensitive ◽  
Wafer Level ◽  
Top Down ◽  
Access Memory ◽  
Transmission Electron ◽  
Contact Processing

Abstract Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.

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