Circuit Edit Geometric Trends

Author(s):  
Michael DiBattista ◽  
Martin Parley ◽  
Don Lyons ◽  
Roddy Cruz ◽  
Alan Wu ◽  
...  

Abstract Focused ion beam (FIB) tools for backside circuit edit play a major role in the validation of integrated circuit (IC) design modifications. Process scaling is one of many significant challenges, because it reduces the accessible area to modify transistors and IC interconnects in the design. This paper examines the geometries available for FIB nanomachining, via milling/etching, and deposited metal jumpers by analyzing polygon data from computer aided design (CAD) virtual layers gathered across four process technologies, from 180nm down to 28nm. The results of this analysis demonstrate that the combination of silicon nanomachining box length and FIB via box length identifies the most challenging aspects of the FIB edit. The smallest geometries include a 300 nanometer silicon access area with a FIB milled 200 nanometer via inside it. More advanced technology nodes will require the ability to make smaller geometries without the help of integrated design features typically referred to as design for FIB/Debug.

Author(s):  
Ankush Oberai ◽  
Rupa Kamoji ◽  
Arpan Bhattacherjee

Abstract In modern-day semiconductor failure analysis (FA), the need for computer-aided design (CAD) has extended beyond the sole physical layout to a much larger scope of integrated circuit (IC) design data, such as the source schematic and netlist. Due to the improved accuracy of predicted failures reported by test and diagnosis tools, it has become virtually mandatory to correlate the potential failing schematic features (e.g., nets and instances) to their corresponding location on the physical-CAD layout and actual device under test (DUT). This paper covers the latest advancements of utilizing IC design schematics for fast and accurate fault localization; along with some of the most-effective methodologies for efficient root-cause analysis.


Author(s):  
Valery Ray ◽  
Ali Hadjikhani ◽  
Joseph Favata ◽  
Seyedeh Ahmadi ◽  
Sina Shahbazmohamadi

Abstract Widespread adoption and significant developments in Focused Ion Beam technology has made FIB/SEM instrumentation a commonplace sample preparation tool. Fundamental limitations inherent to Ga ion species complicate usage of Ga+ FIB instruments for the modification of semiconductor devices on advanced technology nodes. Said limitations are fueling interest in exploring alternative primary species and ion beam technologies for circuit edit applications. Exploratory tests of etching typical semiconductor materials with Xe ion beams generated from two plasma ion sources confirmed advantages of Xe+ as a potential ion species for gas-assisted etching of semiconductor materials, but also revealed potential complications including, swelling of metal and Xe+ retention within the material arising from excessive Xe ion beam current density.


2018 ◽  
Author(s):  
Steve Wang ◽  
Jim McGinn ◽  
Peter Tvarozek ◽  
Amir Weiss

Abstract Secondary electron detector (SED) plays a vital role in a focused ion beam (FIB) system. A successful circuit edit requires a good effective detector. Novel approach is presented in this paper to improve the performance of such a detector, making circuit altering for the most advanced integrated circuit (IC) possible.


Author(s):  
E. Hendarto ◽  
S.L. Toh ◽  
J. Sudijono ◽  
P.K. Tan ◽  
H. Tan ◽  
...  

Abstract The scanning electron microscope (SEM) based nanoprobing technique has established itself as an indispensable failure analysis (FA) technique as technology nodes continue to shrink according to Moore's Law. Although it has its share of disadvantages, SEM-based nanoprobing is often preferred because of its advantages over other FA techniques such as focused ion beam in fault isolation. This paper presents the effectiveness of the nanoprobing technique in isolating nanoscale defects in three different cases in sub-100 nm devices: soft-fail defect caused by asymmetrical nickel silicide (NiSi) formation, hard-fail defect caused by abnormal NiSi formation leading to contact-poly short, and isolation of resistive contact in a large electrical test structure. Results suggest that the SEM based nanoprobing technique is particularly useful in identifying causes of soft-fails and plays a very important role in investigating the cause of hard-fails and improving device yield.


Author(s):  
C. Rue ◽  
S. Herschbein ◽  
C. Scrudato ◽  
L. Fischer ◽  
A. Shore

Abstract The efficiency of Gas-Assisted Etching (GAE) and depositions performed using the Focused Ion Beam (FIB) technique is subject to numerous factors. Besides the wellknown primary parameters recommended by the FIB manufacturer (pixel spacing, dwell time, and gas pressures), certain secondary factors can also have a pronounced effect on the quality of these gas-assisted FIB operations. The position of the gas delivery nozzle during XeF2 mills on silicon is examined and was found to affect both the milling speed and the texture on the floor of the FIB trench. Limitations arising from the memory capacity of the FIB computer can also influence process times and trench quality. Exposing the FIB vacuum chamber to TMCTS during SiO2 depositions is found to temporarily impede the performance of subsequent tungsten depositions, especially following heavy or prolonged TMCTS exposure. A delay period may be required to achieve optimal tungsten depositions following TMCTS use. Finally, the focusing conditions of the ion beam are found to have a significant impact on the resistance of FIB-deposited metal films. This effect is attributed to partial milling of the deposition film due to the intense current density of the collimated ion beam. The resistances of metal depositions performed with intentionally defocused ion beams were found to be lower than those performed with focused beams.


Author(s):  
Ching Shan Sung ◽  
Hsiu Ting Lee ◽  
Jian Shing Luo

Abstract Transmission electron microscopy (TEM) plays an important role in the structural analysis and characterization of materials for process evaluation and failure analysis in the integrated circuit (IC) industry as device shrinkage continues. It is well known that a high quality TEM sample is one of the keys which enables to facilitate successful TEM analysis. This paper demonstrates a few examples to show the tricks on positioning, protection deposition, sample dicing, and focused ion beam milling of the TEM sample preparation for advanced DRAMs. The micro-structures of the devices and samples architectures were observed by using cross sectional transmission electron microscopy, scanning electron microscopy, and optical microscopy. Following these tricks can help readers to prepare TEM samples with higher quality and efficiency.


Author(s):  
Romain Desplats ◽  
Timothee Dargnies ◽  
Jean-Christophe Courrege ◽  
Philippe Perdu ◽  
Jean-Louis Noullet

Abstract Focused Ion Beam (FIB) tools are widely used for Integrated Circuit (IC) debug and repair. With the increasing density of recent semiconductor devices, FIB operations are increasingly challenged, requiring access through 4 or more metal layers to reach a metal line of interest. In some cases, accessibility from the front side, through these metal layers, is so limited that backside FIB operations appear to be the most appropriate approach. The questions to be resolved before starting frontside or backside FIB operations on a device are: 1. Is it do-able, are the metal lines accessible? 2. What is the optimal positioning (e.g. accessing a metal 2 line is much faster and easier than digging down to a metal 6 line)? (for the backside) 3. What risk, time and cost are involved in FIB operations? In this paper, we will present a new approach, which allows the FIB user or designer to calculate the optimal FIB operation for debug and IC repair. It automatically selects the fastest and easiest milling and deposition FIB operations.


Author(s):  
Chin Kai Liu ◽  
Chi Jen. Chen ◽  
Jeh Yan.Chiou ◽  
David Su

Abstract Focused ion beam (FIB) has become a useful tool in the Integrated Circuit (IC) industry, It is playing an important role in Failure Analysis (FA), circuit repair and Transmission Electron Microscopy (TEM) specimen preparation. In particular, preparation of TEM samples using FIB has become popular within the last ten years [1]; the progress in this field is well documented. Given the usefulness of FIB, “Artifact” however is a very sensitive issue in TEM inspections. The ability to identify those artifacts in TEM analysis is an important as to understanding the significance of pictures In this paper, we will describe how to measure the damages introduced by FIB sample preparation and introduce a better way to prevent such kind of artifacts.


Author(s):  
C.H. Wang ◽  
S.P. Chang ◽  
C.F. Chang ◽  
J.Y. Chiou

Abstract Focused ion beam (FIB) is a popular tool for physical failure analysis (FA), especially for circuit repair. FIB is especially useful on advanced technology where the FIB is used to modify the circuit for new layout verification or electrical measurement. The samples are prepared till inter-metal dielectric (IMD), then a hole is dug or a metal is deposited or oxide is deposited by FIB. A common assumption is made that metal under oxide can not be seen by FIB. But a metal ion image is desired for further action. Dual beam, FIB and Scanning Electron Microscope (SEM), tools have a special advantage. When switching back and forth from SEM to FIB the observation has been made that the metal lines can be imaged. The details of this technique will be discussed below.


Author(s):  
K. N. Hooghan ◽  
K. S. Wills ◽  
P.A. Rodriguez ◽  
S.J. O’Connell

Abstract Device repair using Focused Ion Beam(FIB) systems has been in use for most of the last decade. Most of this has been done by people who have been essentially self-taught. The result has been a long learning curve to become proficient in device repair. Since a great deal of the problem is that documentation on this “art form” is found in papers from many different disciplines, this work attempts to summarize all of the available information under one title. The primary focus of FIB device repair is to ensure and maintain device integrity and subsequently retain market share while optimizing the use of the instrument, usually referred to as ‘beam time’. We describe and discuss several methods of optimizing beam time. First, beam time should be minimized while doing on chip navigation to reach the target areas. Several different approaches are discussed: dead reckoning, 3-point alignment, CAD-based navigation, and optical overlay. Second, after the repair areas are located and identified, the desired metal levels must be reached using a combination of beam currents and gas chemistries, and then filled up and strapped to make final connections. Third, cuts and cleanups must be performed as required for the final repair. We will discuss typical values of the beam currents required to maintain device integrity while concurrently optimizing repair time. Maintaining device integrity is difficult because of two potentially serious interactions of the FIB on the substrate: 1) since the beam consists of heavy metal ions (typically Gallium) the act of imaging the surface produces some physical damage; 2) the beam is positively charged and puts some charge into the substrate, making it necessary to use great care working in and around capacitors or active areas such as transistors, in order to avoid changing the threshold voltage of the devices. Strategies for minimizing potential damage and maximizing quality and throughput will be discussed.


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