Advanced T-LSIM System Detections using Amplified External Isolated Source-Sense Unit

2018 ◽  
Author(s):  
Zhi Jie Lau ◽  
Chris Philips
Keyword(s):  
Fault Isolation ◽  
Isolation Technique ◽  
Laser Signal ◽  
Signal Injection ◽  
Sense Unit ◽  
Types Of Faults

Abstract Thermal-Laser Signal Injection Microscopy (T-LSIM) is a widely used fault isolation technique. Although there are several T-LSIM systems on the market, each is limited in terms of the voltage and current it can produce. In this paper, the authors explain how they incorporated an Amplified External Isolated Source-Sense (AxISS) unit into their T-LSIM platform, increasing its current sourcing capability and voltage biasing range. They also provide examples highlighting the types of faults and failures that the modified system can detect.

Case Study in Fault Isolation of a Metal Short for Yield Enhancement

2010 ◽  
Author(s):  
Sarven Ipek ◽  
David Grosjean
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Photon Emission ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Analysis Technique ◽  
Laser Signal ◽  
Signal Injection ◽  
Microscopy Techniques

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.

In-SEM Fault Isolation Using Voltage Contrast, EBIC/EBAC and Resistive Contrast Imaging

2020 ◽  
Author(s):  
Lori L. Sarnecki ◽  
Caleb Daigneault
Keyword(s):  
Semiconductor Device ◽  
Photon Emission ◽  
Fault Localization ◽  
Spot Size ◽  
Fault Isolation ◽  
Contrast Imaging ◽  
Laser Signal ◽  
Signal Injection ◽  
Voltage Contrast ◽  
Optical Level

Abstract With the ever shrinking semiconductor device features coupled with the increasing circuit density, optical level fault localization techniques such as Photon Emission Microscopy (PEM), Laser Signal Injection Microscopy (LSIM) and Thermal Hotspot Localization (THS) can only get you so far due to these limitations: magnification, spot size and drop in detection sensitive at higher magnification. Using a 100x objective can put you in the ball park. Test data such as ATE & ATPG can point you to a specific block of circuitry but still far from defect localization. With in-SEM fault isolation and localization techniques such as Voltage Contrast (VC), Electron Beam Induced/Absorb Current (EBIC/EBAC) and Resistive Contrast Imaging (RCI), the nano-scale defect can be further localized due to the advantage of the magnification and spot size. This paper offers the combined techniques of optical level fault localization (PEM, LSIM & THS) and in- SEM or E-beam techniques (VC, EBAC, RCI) to successfully perform fault localization when challenged with the above scenarios.

New Applications of Thermal Laser Signal Injection Microscopy (T-LSIM)

2003 ◽  
Author(s):  
R. Aaron Falk ◽  
Neil Bauersfeld ◽  
Mark LaPierre ◽  
Shawn Elliott
Keyword(s):  
Integrated Circuits ◽  
Fault Isolation ◽  
Digital Integrated Circuits ◽  
Leakage Currents ◽  
Isolation Techniques ◽  
Laser Signal ◽  
Signal Injection ◽  
Emission Microscopy ◽  
New Applications ◽  
Analytical Power

Abstract Thermal laser signal injection microscopy (T-LSIM) (aka TIVA and OBIRCH) has shown considerable promise in stateof- the-art digital integrated circuits. The technique has been utilized to locate shorts, leakage currents, problem vias, and timing issues in these devices. However, little has been published on the utility of this technique for analog and mixed signal devices. In this paper we demonstrate the application of T-LSIM on two different analog devices with defects that conventional FA technology and fault isolation techniques were unable to locate. Analog devices produce several unique challenges to the basic T-LSIM technique as typically utilized in the digital regime. Extensions of the basic T-LSIM technique were utilized to locate the failures, which produced unexpected results. The T-LSIM technique has proved essential in the quick identification and localization of failure sites. The T-LSIM technique provides the failure analyst with the analytical power not previously available on conventional fault isolation tools such as emission microscopy and liquid crystal.

Fault Isolation of MOL and FEOL Buried Defects Using Conductive Atomic Force Microscopy as a Complement to Passive Voltage Contrast Imaging

2017 ◽  
Author(s):  
Lucile C. Teague Sheridan ◽  
Linda Conohan ◽  
Chong Khiam Oh
Keyword(s):  
Atomic Force Microscopy ◽  
Cmos Technology ◽  
Fault Isolation ◽  
Contrast Imaging ◽  
Conductive Atomic Force Microscopy ◽  
Isolation Technique ◽  
Conductive Afm ◽  
Force Microscopy ◽  
Atomic Force ◽  
Voltage Contrast

Abstract Atomic force microscopy (AFM) methods have provided a wealth of knowledge into the topographic, electrical, mechanical, magnetic, and electrochemical properties of surfaces and materials at the micro- and nanoscale over the last several decades. More specifically, the application of conductive AFM (CAFM) techniques for failure analysis can provide a simultaneous view of the conductivity and topographic properties of the patterned features. As CMOS technology progresses to smaller and smaller devices, the benefits of CAFM techniques have become apparent [1-3]. Herein, we review several cases in which CAFM has been utilized as a fault-isolation technique to detect middle of line (MOL) and front end of line (FEOL) buried defects in 20nm technologies and beyond.

Fault Localization of Power-Ground Short via Signal Injection and Oscilloscope Technique

2010 ◽  
Author(s):  
Binh Nguyen
Keyword(s):  
Low Cost ◽  
Short Circuit ◽  
Fault Localization ◽  
Fault Isolation ◽  
Test Apparatus ◽  
Good Working ◽  
Signal Injection ◽  
Set Up ◽  
Non Destructive ◽  
Short Circuit Condition

Abstract For those attempting fault isolation on computer motherboard power-ground short issues, the optimal technique should utilize existing test equipment available in the debug facility, requiring no specialty equipment as well as needing a minimum of training to use effectively. The test apparatus should be both easy to set up and easy to use. This article describes the signal injection and oscilloscope technique which meets the above requirements. The signal injection and oscilloscope technique is based on the application of Ohm's law in a short-circuit condition. Two experiments were conducted to prove the effectiveness of these techniques. Both experiments simulate a short-circuit condition on the VCC3 power rail of a good working PC motherboard and then apply the signal injection and oscilloscope technique to localize the short. The technique described is a simple, low cost and non-destructive method that helps to find the location of the power-ground short quickly and effectively.

WLCSP Laminate Removal Using NIR Laser

2018 ◽  
Author(s):  
Chun Haur Khoo
Keyword(s):  
Near Infrared ◽  
Laser Energy ◽  
Photon Emission ◽  
Mechanical Damage ◽  
Consumer Products ◽  
Fault Isolation ◽  
Wafer Level ◽  
Isolation Technique ◽  
Laminate Layer ◽  
Nir Laser

Abstract Driven by the cost reduction and miniaturization, Wafer Level Chip Scale Packaging (WLCSP) has experienced significant growth mainly driven by mobile consumer products. Depending on the customers or manufacturing needs, the bare silicon backside of the WLCSP may be covered with a backside laminate layer. In the failure analysis lab, in order to perform the die level backside fault isolation technique using Photon Emission Microscope (PEM) or Laser Signal Injection Microscope (LSIM), the backside laminate layer needs to be removed. Most of the time, this is done using the mechanical polishing method. This paper outlines the backside laminate removal method of WLCSP using a near infrared (NIR) laser that produces laser energy in the 1,064 nm range. This method significantly reduces the sample preparation time and also reduces the risk of mechanical damage as there is no application of mechanical force. This is an effective method for WLCSP mounted on a PCB board.

A Novel OBIRCH Fault Isolation Method to Locate the Leakage Failure Point

2008 ◽  
Author(s):  
Chi-Lin Huang ◽  
Yu Hsiang Shu
Keyword(s):  
Semiconductor Device ◽  
Fault Isolation ◽  
Resistance Change ◽  
Cross Sectional ◽  
Isolation Technique ◽  
Isolation Techniques ◽  
Atomic Force ◽  
Analysis Experiment ◽  
Failure Point ◽  
Leakage Failure

Abstract Conventional isolation techniques, such as Optical Beam Induced Resistance Change (OBIRCH) or photoemission microscopy (PEM) frequently fail to locate failure points when only applied to power pin of the semiconductor device. In this paper, a novel OBIRCH failure isolation technique is utilized to detect leakage failures. Different test conditions are presented to identify the differences in current when all input pins are pulled high in an OBIRCH system. In order to verify a failure point, it is necessary to perform electrical analysis of the suspected failure point in the failing sample. In general, Conductive Atomic Force Microscope (C-AFM) and a Nano-Prober is sufficient to provide the electrical data required for failure analysis. Experiment results, however, prove that this novel OBIRCH failure isolation technique is effective in locating the failure point, especially for leakage failures. The failure mechanism is illustrated using cross-sectional TEM.

Pseudo-Dynamic Fault Isolation Technique Using Backside Emission Microscopy – Case Study, Where All Other Methods Fail

2002 ◽  
Author(s):  
Yoav Weizman ◽  
Ezra Baruch ◽  
Michael Zimin
Keyword(s):  
Failure Analysis ◽  
Process Variations ◽  
Fault Isolation ◽  
Operating Conditions ◽  
Detection Sensitivity ◽  
Isolation Technique ◽  
Root Cause ◽  
Emission Microscopy ◽  
Failure Location ◽  
Noisy Background

Abstract Emission microscopy is usually implemented for static operating conditions of the DUT. Under dynamic operation it is nearly impossible to identify a failure out of the noisy background. In this paper we describe a simple technique that could be used in cases where the temporal location of the failure was identified however the physical location is not known or partially known. The technique was originally introduced to investigate IDDq failures (1) in order to investigate timing related issues with automated tester equipment. Ishii et al (2) improved the technique and coupled an emission microscope to the tester for functional failure analysis of DRAMs and logic LSIs. Using consecutive step-by-step tester halting coupled to a sensitive emission microscope, one is able detect the failure while it occurs. We will describe a failure analysis case in which marginal design and process variations combined to create contention at certain logic states. Since the failure occurred arbitrarily, the use of the traditional LVP, that requires a stable failure, misled the analysts. Furthermore, even if we used advanced tools as PICA, which was actually designed to locate such failures, we believe that there would have been little chance of observing the failure since the failure appeared only below 1.3V where the PICA tool has diminished photon detection sensitivity. For this case the step-by-step halting technique helped to isolate the failure location after a short round of measurements. With the use of logic simulations, the root cause of the failure was clear once the failing gate was known.

Advanced Fault Isolation Technique Using Electro-Optical Terahertz Pulse Reflectometry (EOTPR) for 2D and 2.5D Flip-Chip Package

2012 ◽  
Author(s):  
Lihong Cao ◽  
Manasa Venkata ◽  
Meng Yeow Tay ◽  
Wen Qiu ◽  
J. Alton ◽  
...  
Keyword(s):  
Time Domain ◽  
Flip Chip ◽  
Time Domain Reflectometry ◽  
Fault Isolation ◽  
Experimental Results ◽  
Terahertz Pulse ◽  
Isolation And Identification ◽  
Isolation Technique ◽  
Non Destructive

Abstract Electro-optical terahertz pulse reflectometry (EOTPR) was introduced last year to isolate faults in advanced IC packages. The EOTPR system provides 10μm accuracy that can be used to non-destructively localize a package-level failure. In this paper, an EOTPR system is used for non-destructive fault isolation and identification for both 2D and 2.5D with TSV structure of flip-chip packages. The experimental results demonstrate higher accuracy of the EOTPR system in determining the distance to defect compared to the traditional time-domain reflectometry (TDR) systems.

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