Residual EG Oxide in FinFET Analyses and Its Impact to Yield, Product Performance, and Transistor Reliability

2019 ◽  
Author(s):  
Pat McGinnis ◽  
Dave Albert ◽  
Zhigang Song ◽  
Johns Oarethu ◽  
Phong Tran ◽  
...  
Keyword(s):  
Failure Analysis ◽  
High Performance ◽  
Performance Degradation ◽  
Product Performance ◽  
Temperature Instability ◽  
Bias Temperature Instability ◽  
Analysis Methodology ◽  
Quantum Nature ◽  
Transistor Reliability ◽  
Stress Experiment

Abstract This paper describes an electrical and physical failure analysis methodology leading to a unique defect called residual EG oxide (shortened to REGO); which manifested in 14nm SOI high performance FinFET technology. Theoretically a REGO defect can be present anywhere and on any multiple Fin transistor, or any type of device (low Vt, Regular Vt or High Vt). Because of the quantum nature of the FinFET and REGO occurrence being primarily limited to single Fins, this defect does not impact large transistors with multiple FINs; moreover, REGO was found to only impact 3 Fin or less transistors. Since REGO can be present on any multi-FIN transistor the potential does exist for the defect to escape test screening. Subsequently a reliability BTI (Bias Temperature Instability) stress experiment by nanoprobing at contact level was designed to assess REGO’s potential reliability impact. The BTI stress results indicate that the REGO defect would not result in any additional reliability or performance degradation beyond model expectations.

Lithium-ion Battery Degradation Mechanisms and Failure Analysis Methodology

2012 ◽  
Author(s):  
Bhanu Sood ◽  
Lucas Severn ◽  
Michael Osterman ◽  
Michael Pecht ◽  
Anton Bougaev ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Lithium Ion Batteries ◽  
Elevated Temperatures ◽  
Failure Process ◽  
Lithium Ion ◽  
Degradation Mechanisms ◽  
Analysis Methodology ◽  
Depth Of Discharge ◽  
Battery Degradation ◽  
Non Destructive

Abstract A review of the prevalent degradation mechanisms in Lithium ion batteries is presented. Degradation and eventual failure in lithium-ion batteries can occur for a variety of dfferent reasons. Degradation in storage occurs primarily due to the self-discharge mechanisms, and is accelerated during storage at elevated temperatures. The degradation and failure during use conditions is generally accelerated due to the transient power requirements, the high frequency of charge/discharge cycles and differences between the state-of-charge and the depth of discharge influence the degradation and failure process. A step-by-step methodology for conducting a failure analysis of Lithion batteries is presented. The failure analysis methodology is illustrated using a decision-tree approach, which enables the user to evaluate and select the most appropriate techniques based on the observed battery characteristics. The techniques start with non-destructive and non-intrusive steps and shift to those that are more destructive and analytical in nature as information about the battery state is gained through a set of measurements and experimental techniques.

Application of Conductive-AFM in Soft Failure Analysis

2017 ◽  
Author(s):  
Chuan Zhang ◽  
Yinzhe Ma ◽  
Gregory Dabney ◽  
Oh Chong Khiam ◽  
Esther P.Y. Chen
Keyword(s):  
Failure Analysis ◽  
Conductive Atomic Force Microscopy ◽  
Test Parameter ◽  
Conductive Afm ◽  
Force Microscopy ◽  
Analysis Methodology ◽  
Soft Failure ◽  
Atomic Force ◽  
Test Conditions ◽  
Sensitive Characteristics

Abstract Soft failures are among the most challenging yield detractors. They typically show test parameter sensitive characteristics, which would pass under certain test conditions but fail under other conditions. Conductive-atomic force microscopy (CAFM) emerged as an ideal solution for soft failure analysis that can balance the time and thoroughness. By inserting CAFM into the soft failure analysis flow, success rate of such type of analysis can be significantly enhanced. In this paper, a logic chain soft failure and a SRAM local bitline soft failure are used as examples to illustrate how this failure analysis methodology provides a powerful and efficient solution for soft failure analysis.

Failure Analysis Enhancement by Incorporating a Compact Scan Diagnosis System

2014 ◽  
Author(s):  
Rommel Estores ◽  
Pascal Vercruysse ◽  
Karl Villareal ◽  
Eric Barbian ◽  
Ralph Sanchez ◽  
...  
Keyword(s):  
Data Analysis ◽  
Failure Analysis ◽  
Real Analysis ◽  
Failure Data ◽  
Analysis Methodology ◽  
Efficiency And Effectiveness ◽  
Scan Chain ◽  
On Chip ◽  
Analysis Environment ◽  
Selection Of

Abstract The failure analysis community working on highly integrated mixed signal circuitry is entering an era where simultaneously System-On-Chip technologies, denser metallization schemes, on-chip dissipation techniques and intelligent packages are being introduced. These innovations bring a great deal of defect accessibility challenges to the failure analyst. To contend in this era while aiming for higher efficiency and effectiveness, the failure analysis environment must undergo a disruptive evolution. The success or failure of an analysis will be determined by the careful selection of tools, data and techniques in the applied analysis flow. A comprehensive approach is required where hardware, software, data analysis, traditional FA techniques and expertise are complementary combined [1]. This document demonstrates this through the incorporation of advanced scan diagnosis methods in the overall analysis flow for digital functionality failures and supporting the enhanced failure analysis methodology. For the testing and diagnosis of the presented cases, compact but powerful scan test FA Lab hardware with its diagnosis software was used [2]. It can therefore easily be combined with the traditional FA techniques to provide stimulus for dynamic fault localizations [3]. The system combines scan chain information, failure data and layout information into one viewing environment which provides real analysis power for the failure analyst. Comprehensive data analysis is performed to identify failing cells/nets, provide a better overview of the failure and the interactions to isolate the fault further to a smaller area, or to analyze subtle behavior patterns to find and rationalize possible faults that are otherwise not detected. Three sample cases will be discussed in this document to demonstrate specific strengths and advantages of this enhanced FA methodology.

Device Selection for Failure Analysis of Chain Fails Using Diagnosis Driven Yield Analysis

2011 ◽  
Author(s):  
Chris Schuermyer ◽  
Brady Benware ◽  
Graham Rhodes ◽  
Davide Appello ◽  
Vincenzo Tancorre ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Yield Analysis ◽  
Analysis Methodology ◽  
Device Selection ◽  
Selection For ◽  
Random Defects

Abstract This work presents the first application of a diagnosis driven approach for identifying systematic chain fail defects in order to reduce the time spent in failure analysis. The zonal analysis methodology that is applied separates devices into systematic and random populations of chain fails in order to prevent submitting random defects for failure analysis. Two silicon case studies are presented to validate the production worthiness of diagnosis driven yield analysis for chain fails. The defects uncovered in these case studies are very subtle and would be difficult to identify with any other methodology.

Sub-20nm Device Voltage-Sensitive SRAM Characterization and Failure Analysis

2018 ◽  
Author(s):  
Seng Nguon Ting ◽  
Hsien-Ching Lo ◽  
Donald Nedeau ◽  
Aaron Sinnott ◽  
Felix Beaudoin
Keyword(s):  
Failure Analysis ◽  
High Performance ◽  
Yield Loss ◽  
Technology Development ◽  
High Density ◽  
High K ◽  
Yield Learning ◽  
Oxide Deposition ◽  
Edge Profile ◽  
High K Dielectric

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.

Unique Autoclave Stress Induced Failure Mechanism

2005 ◽  
Author(s):  
John Butchko ◽  
Bruce T. Gillette
Keyword(s):  
Corrosion Rate ◽  
Grain Boundary ◽  
Failure Analysis ◽  
Failure Mechanism ◽  
Metal Corrosion ◽  
Corrosion Mechanism ◽  
Reliability Testing ◽  
Process Change ◽  
Transistor Reliability ◽  
Pass Through

Abstract Autoclave Stress failures were encountered at the 96 hour read during transistor reliability testing. A unique metal corrosion mechanism was found during the failure analysis, which was creating a contamination path to the drain source junction, resulting in high Idss and Igss leakage. The Al(Si) top metal was oxidizing along the grain boundaries at a faster rate than at the surface. There was subsurface blistering of the Al(Si), along with the grain boundary corrosion. This blistering was creating a contamination path from the package to the Si surface. Several variations in the metal stack were evaluated to better understand the cause of the failures and to provide a process solution. The prevention of intergranular metal corrosion and subsurface blistering during autoclave testing required a materials change from Al(Si) to Al(Si)(Cu). This change resulted in a reduced corrosion rate and consequently prevented Si contamination due to blistering. The process change resulted in a successful pass through the autoclave testing.

Failure Analysis of Functional Failures in a Designed for FA SRAM

2004 ◽  
Author(s):  
Gil Garteiz
Keyword(s):  
Failure Analysis ◽  
Success Rate ◽  
Physical Analysis ◽  
Analysis Methodology

Abstract Designing devices for failure analisys (FA) is becoming increasingly critical as structure geometries and killer defects rapidly decrease in size. Naturally, devices that are designed for FA are much easier to analyze and have a higher FA success rate than those that are not. Several analyses of functional failures in a 0.18um CMOS SRAM are presented in this paper to demonstrate “Design For FA” usefulness and application. Physical analysis methodology is also discussed.

scholarly journals Optimization of a Low-Power Chemoresistive Gas Sensor: Predictive Thermal Modelling and Mechanical Failure Analysis

Sensors ◽  
2021 ◽  
Vol 21 (3) ◽  
pp. 783 ◽  
Author(s):  
Andrea Gaiardo ◽  
David Novel ◽  
Elia Scattolo ◽  
Michele Crivellari ◽  
Antonino Picciotto ◽  
...  
Keyword(s):  
Low Power ◽  
Failure Analysis ◽  
Gas Sensors ◽  
High Performance ◽  
Gas Sensing ◽  
Mechanical Failure ◽  
Sensing Applications ◽  
Theoretical Approaches ◽  
Sensing Material ◽  
Silicon Bulk

The substrate plays a key role in chemoresistive gas sensors. It acts as mechanical support for the sensing material, hosts the heating element and, also, aids the sensing material in signal transduction. In recent years, a significant improvement in the substrate production process has been achieved, thanks to the advances in micro- and nanofabrication for micro-electro-mechanical system (MEMS) technologies. In addition, the use of innovative materials and smaller low-power consumption silicon microheaters led to the development of high-performance gas sensors. Various heater layouts were investigated to optimize the temperature distribution on the membrane, and a suspended membrane configuration was exploited to avoid heat loss by conduction through the silicon bulk. However, there is a lack of comprehensive studies focused on predictive models for the optimization of the thermal and mechanical properties of a microheater. In this work, three microheater layouts in three membrane sizes were developed using the microfabrication process. The performance of these devices was evaluated to predict their thermal and mechanical behaviors by using both experimental and theoretical approaches. Finally, a statistical method was employed to cross-correlate the thermal predictive model and the mechanical failure analysis, aiming at microheater design optimization for gas-sensing applications.

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