Simple Circuit Edit Passive Voltage Contrast Technique to Identify Leakage Location

Author(s):  
S.L. Ting ◽  
P.K. Tan ◽  
I. Withana ◽  
H. Tan ◽  
C.Q. Chen

Abstract Passive voltage contrast (PVC) is widely used to detect underlying connectivity issues between metals based on the brightness of upper metals using scanning electron microscopy (SEM) or focused ion beam (FIB). [1] However, it cannot be applied in all cases due to the uniqueness of each case where brightness alone is insufficient to tell leakage location. In this study, propose a simple technique using platinum (Pt) marking as a circuit edit (CE) technique to alter metal PVC to identify the actual leakage location. Conventional SEM and PVC contrast imaging are unable to pinpoint exact defects without data confirming the leakage from nano-probing such as Atomic Force Probing (AFP) or SEM base nano-probing (NP) [2]. Using this method, we can improve the analysis cycle time by direct analysts the defective location in SEM, while also saving tool cost.

Author(s):  
H. Lorenz ◽  
C. Engel

Abstract Due to the continuously decreasing cell size of DRAMs and concomitantly diminishing thickness of some insulating layers new failure mechanisms appear which until now had no significance for the cell function. For example high resistance leakage paths between closely spaced conductors can lead to retention problems. These are hard to detect by electrical characterization in a memory tester because the involved currents are in the range of pA. To analyze these failures we exploit the very sensitive passive voltage contrast of the Focused Ion Beam Microscope (FIB). The voltage contrast can further be enhanced by in-situ FIB preparations to obtain detailed information about the failure mechanism. The first part of this paper describes a method to detect a leakage path between a borderless contact on n-diffusion and an adjacent floating gate by passive voltage contrast achieved after FIB circuit modification. In the second part we will demonstrate the localization of a DRAM trench dielectric breakdown. In this case the FIB passive voltage contrast technique is not limited to the localization of the failing trench. We can also obtain the depth of the leakage path by selective insitu etching with XeF2 stopped immediately after a voltage contrast change.


Author(s):  
X. Yang ◽  
X. Song

Abstract Novel Focused Ion Beam (FIB) voltage-contrast technique combined with TEM has been used in this study to identify a certain subtle defect mechanism that caused reliability stress failures of a new product. The suspected defect was first isolated to a unique via along the row through electrical testing and layout analysis. Static voltage contrast of FIB cross-section was used to confirm the suspected open defect at the via. Precision Transmission Electron Microscope (TEM) was then used to reveal the detail of the defect. Based on the result, proper process changes were implemented. The failure mode was successfully eliminated and the reliability of the product was greatly improved.


2005 ◽  
Vol 38 (6) ◽  
pp. 2368-2375 ◽  
Author(s):  
Nick Virgilio ◽  
Basil D. Favis ◽  
Marie-France Pépin ◽  
Patrick Desjardins ◽  
Gilles L'Espérance

Author(s):  
A.Y. Liang ◽  
P. Tangyunyong ◽  
R.S. Bennett ◽  
R.S. Flores ◽  
J.M. Soden ◽  
...  

Abstract We present the results of recent failure analysis of an advanced, 0.5 um, fully planarized, triple metallization CMOS technology. A variety of failure analysis (FA) tools and techniques were used to localize and identify defects generated by wafer processing. These include light (photon) emission microscopy (LE), fluorescent microthermal imaging (FMI), focused ion beam cross sectioning, SEM/voltage contrast imaging, resistive contrast imaging (RCI), and e-beam testing using an IDS-5000 with an HP 82000. The defects identified included inter- and intra-metal shorts, gate oxide shorts due to plasma processing damage, and high contact resistance due to the contact etch and deposition process. Root causes of these defects were determined and corrective action was taken to improve yield and reliability.


2002 ◽  
Vol 719 ◽  
Author(s):  
Myoung-Woon Moon ◽  
Kyang-Ryel Lee ◽  
Jin-Won Chung ◽  
Kyu Hwan Oh

AbstractThe role of imperfections on the initiation and propagation of interface delaminations in compressed thin films has been analyzed using experiments with diamond-like carbon (DLC) films deposited onto glass substrates. The surface topologies and interface separations have been characterized by using the Atomic Force Microscope (AFM) and the Focused Ion Beam (FIB) imaging system. The lengths and amplitudes of numerous imperfections have been measured by AFM and the interface separations characterized on cross sections made with the FIB. Chemical analysis of several sites, performed using Auger Electron Spectroscopy (AES), has revealed the origin of the imperfections. The incidence of buckles has been correlated with the imperfection length.


Author(s):  
Lucile C. Teague Sheridan ◽  
Linda Conohan ◽  
Chong Khiam Oh

Abstract Atomic force microscopy (AFM) methods have provided a wealth of knowledge into the topographic, electrical, mechanical, magnetic, and electrochemical properties of surfaces and materials at the micro- and nanoscale over the last several decades. More specifically, the application of conductive AFM (CAFM) techniques for failure analysis can provide a simultaneous view of the conductivity and topographic properties of the patterned features. As CMOS technology progresses to smaller and smaller devices, the benefits of CAFM techniques have become apparent [1-3]. Herein, we review several cases in which CAFM has been utilized as a fault-isolation technique to detect middle of line (MOL) and front end of line (FEOL) buried defects in 20nm technologies and beyond.


Author(s):  
Natsuko Asano ◽  
Shunsuke Asahina ◽  
Natasha Erdman

Abstract Voltage contrast (VC) observation using a scanning electron microscope (SEM) or a focused ion beam (FIB) is a common failure analysis technique for semiconductor devices.[1] The VC information allows understanding of failure localization issues. In general, VC images are acquired using secondary electrons (SEs) from a sample surface at an acceleration voltage of 0.8–2.0 kV in SEM. In this study, we aimed to find an optimized electron energy range for VC acquisition using Auger electron spectroscopy (AES) for quantitative understanding.


Author(s):  
Z. G. Song ◽  
S. K. Loh ◽  
X. H. Zheng ◽  
S.P. Neo ◽  
C. K. Oh

Abstract This article presents two cases to demonstrate the application of focused ion beam (FIB) circuit edit in analysis of memory failure of silicon on insulator (SOI) devices using XTEM and EDX analyses. The first case was a single bit failure of SRAM units manufactured with 90 nm technology in SOI wafer. The second case was the whole column failure with a single bit pass for a SRAM unit. From the results, it was concluded that FIB circuit edit and electrical characterization is a good methodology for further narrowing down the defective location of memory failure, especially for SOI technology, where contact-level passive voltage contrast is not suitable.


Author(s):  
Randal E. Mulder ◽  
Sam Subramanian ◽  
Tony Chrastecky

Abstract Atomic force probing (AFP) uses very sharp tungsten tips (100nm in radius) which wear out rather quickly, even with the greater durability of tungsten as compared to silicon. This paper demonstrates how worn tips that no longer image and probe properly can be reconditioned using the focus ion beam (FIB) tool. The method works best for tips that are under approx. 750nm in diameter and are not bent. It works well for freshly manufactured tips that do not work properly due to mishandling or improper storage which allowed particulates/oxide to build up on the tip. The method also works well for fresh tips that have been worn down (or slightly bent) after several hours of scanning and probing. This method is straightforward and requires a minimal amount of time. Typically, four probe tips can be reconditioned in about 30 minutes on the FIB.


Author(s):  
Julien Goxe ◽  
Béatrice Vanhuffel ◽  
Marie Castignolles ◽  
Thomas Zirilli

Abstract Passive Voltage Contrast (PVC) in a Scanning Electron Microscope (SEM) or a Focused Ion Beam (FIB) is a key Failure Analysis (FA) technique to highlight a leaky gate. The introduction of Silicon On Insulator (SOI) substrate in our recent automotive analog mixed-signal technology highlighted a new challenge: the Bottom Oxide (BOX) layer, by isolating the Silicon Active Area from the bulk made PVC technique less effective in finding leaky MOSFET gates. A solution involving sample preparation performed with standard FA toolset is proposed to enhance PVC on SOI substrate.


Sign in / Sign up

Export Citation Format

Share Document