scholarly journals Fault Isolation Approaches for Nanoscale TSV Interconnects in 3D Heterogenous Integration

Author(s):  
K.J.P. Jacobs ◽  
A. Jourdain ◽  
I. De Wolf ◽  
E. Beyne

Abstract We report optical and electron beam-based fault isolation approaches for short and open defects in nanometer scale through silicon via (TSV) interconnects (180×250 nm, 500 nm height). Short defects are localized by photon emission microscopy (PEM) and optical beam-induced current (OBIC) techniques, and open defects are isolated by active voltage contrast imaging in the scanning electron microscope (SEM). We confirm our results by transmission electron microscopy (TEM) based cross sectioning.

Author(s):  
Lori L. Sarnecki ◽  
Caleb Daigneault

Abstract With the ever shrinking semiconductor device features coupled with the increasing circuit density, optical level fault localization techniques such as Photon Emission Microscopy (PEM), Laser Signal Injection Microscopy (LSIM) and Thermal Hotspot Localization (THS) can only get you so far due to these limitations: magnification, spot size and drop in detection sensitive at higher magnification. Using a 100x objective can put you in the ball park. Test data such as ATE & ATPG can point you to a specific block of circuitry but still far from defect localization. With in-SEM fault isolation and localization techniques such as Voltage Contrast (VC), Electron Beam Induced/Absorb Current (EBIC/EBAC) and Resistive Contrast Imaging (RCI), the nano-scale defect can be further localized due to the advantage of the magnification and spot size. This paper offers the combined techniques of optical level fault localization (PEM, LSIM & THS) and in- SEM or E-beam techniques (VC, EBAC, RCI) to successfully perform fault localization when challenged with the above scenarios.


Author(s):  
Lucile C. Teague Sheridan ◽  
Linda Conohan ◽  
Chong Khiam Oh

Abstract Atomic force microscopy (AFM) methods have provided a wealth of knowledge into the topographic, electrical, mechanical, magnetic, and electrochemical properties of surfaces and materials at the micro- and nanoscale over the last several decades. More specifically, the application of conductive AFM (CAFM) techniques for failure analysis can provide a simultaneous view of the conductivity and topographic properties of the patterned features. As CMOS technology progresses to smaller and smaller devices, the benefits of CAFM techniques have become apparent [1-3]. Herein, we review several cases in which CAFM has been utilized as a fault-isolation technique to detect middle of line (MOL) and front end of line (FEOL) buried defects in 20nm technologies and beyond.


Author(s):  
M.K. Dawood ◽  
C. Chen ◽  
P.K. Tan ◽  
S. James ◽  
P.S. Limin ◽  
...  

Abstract In this work, we present two case studies on the utilization of advanced nanoprobing on 20nm logic devices at contact layer to identify the root cause of scan logic failures. In both cases, conventional failure analysis followed by inspection of passive voltage contrast (PVC) failed to identify any abnormality in the devices. Technology advancement makes identifying failure mechanisms increasingly more challenging using conventional methods of physical failure analysis (PFA). Almost all PFA cases for 20nm technology node devices and beyond require Transmission Electron Microscopy (TEM) analysis. Before TEM analysis can be performed, fault isolation is required to correctly determine the precise failing location. Isolated transistor probing was performed on the suspected logic NMOS and PMOS transistors to identify the failing transistors for TEM analysis. In this paper, nanoprobing was used to isolate the failing transistor of a logic cell. Nanoprobing revealed anomalies between the drain and bulk junction which was found to be due to contact gouging of different severities.


Author(s):  
Y. N. Hua ◽  
Z. R. Guo ◽  
L. H. An ◽  
Shailesh Redkar

Abstract In this paper, some low yield cases in Flat ROM device (0.45 and 0.6 µm) were investigated. To find killer defects and particle contamination, KLA, bitmap and emission microscopy techniques were used in fault isolation. Reactive ion etching (RIE) and chemical delayering, 155 Wright Etch, BN+ Etch and scanning electron microscope (SEM) were used for identification and inspection of defects. In addition, energy-dispersive X-ray microanalysis (EDX) was used to determine the composition of the particle or contamination. During failure analysis, seven kinds of killer defects and three killer particles were found in Flat ROM devices. The possible root causes, mechanisms and elimination solutions of these killer defects/particles were also discussed.


Author(s):  
A.C.T. Quah ◽  
G.B. Ang ◽  
D. Nagalingam ◽  
C.Q. Chen ◽  
H.P. Ng ◽  
...  

Abstract This paper describes the observation of photoemissions from saturated transistors along a connecting path with open defect in the logic array. By exploiting this characteristic phenomenon to distinguish open related issues, we described with 2 case studies using Photon Emission Microscopy, CAD navigation and layout tracing to identify the ‘open’ failure path. Further layout and EBAC analysis are then employed to effectively localize the failure site.


Author(s):  
Syd Wilson ◽  
Manoj Nair ◽  
Michael Vicker ◽  
Richard B. Meador ◽  
George Smoot ◽  
...  

Abstract First silicon of a cost effective, BICMOS mixed signal RF/IF integrated circuit (IC) for third generation (3G) cellular phones showed high leakage current on the analog receive supply pins in “battery save” mode. Our tasks were to identify and isolate the source of leakage and to fix the design. Alternate debug techniques were used to isolate the cause of the leakage and provide a solution after inconclusive results were obtained using photon emission microscopy,(1) and infrared microthermography techniques.


Author(s):  
David P. Vallett

Abstract This paper presents detailed results of scanning SQUID microscopy (SSM) analyses performed on the frontside and backside of both loose and packaged die. Optical and SEM images of localized defects are shown. Comparisons with alternative physical fault isolation (PFI) techniques like liquid crystal (LC), Schlieren thermal mapping (STM), temperature induced voltage alteration (TIVA), and photon emission microscopy (PEM) are included. Finally, limitations with and potential improvements for die level SSM are also discussed.


1991 ◽  
Vol 224 ◽  
Author(s):  
Tian-Qun Zhou ◽  
Andrzej Buczkowski ◽  
Zbigniew Radzimski ◽  
George A. Rozgonyi

AbstractA study of gettering and electrical activity of metallic impurities Ni, Au and Cu has been carried out on epitaxial Si/Si(2%Ge)/Si wafers containing interfacial misfit dislocations. The impurities were intentionally introduced from a backside deposited thin metal followed by rapid thermal annealing (RTA). Transmission Electron Microscopy (TEM) results indicate that the impurities were gettered along the misfit dislocations in near-surface regions either as Au precipitate colonies, or as NiSi2 and CuSi silicide precipitates. Data from Scanning Electron Microscopy (SEM) in the Electron Beam Induced Current (EBIC) mode revealed that these precipitates dominate the recombination properties of the initially inactive misfit dislocation.


Author(s):  
P.K. Tan ◽  
Z.H. Mai ◽  
Y.W. Goh ◽  
L. Zhu ◽  
S.L. Toh ◽  
...  

Abstract Electrical Test (ET) structures are used to monitor the health and yield of a process line. With the scaling down of semiconductor devices to nanometer ranges, the number of metal lines and vias increase. In order to simulate the electrical performance of devices and to increase the sensitivity for line health check, ET structures are designed to be more complicated with a larger area. Hence, fault isolation and failure analysis become more challenging. In this paper, the combined technique of Scanning Electron Microscope (SEM) Passive Voltage Contrast (PVC), Nanoprobing technique, and Divide and Conquer Method (DCM) are proposed to locate open failure and high resistance failure in an ET via chain.


2006 ◽  
Vol 70 (3) ◽  
pp. 257-264 ◽  
Author(s):  
H.-L. Hong ◽  
J.-X. Mi

AbstractThe mineralogical characteristics of halloysite in rectorite pelite in the Zhongxiang area, Hubei, China, were investigated using X-ray diffraction, scanning electron microscopy and high-resolution transmission electron microscopy methods. The results show that halloysite crystals exhibit euhedral lamellar, tubular or club-like, and needle-like or fibre-like morphologies, indicating that they crystallized from a significantly water-saturated environment. The mineral assemblage of the rectorite pelite is rectorite, halloysite, illite, gypsum, pyrite and rutile, suggesting a weak supergene alteration. Several features related to crystallization of halloysite were noted. Growth of halloysite on rectorite edge surfaces in voids and twins of halloysite on a nanometer scale with composition plane (110) were found in the Zhongxiang rectorite pelite, and, in particular, the tapered ends of tubes suggest that halloysite crystallized from solution. Disaggregation of lamellar halloysite particles into parallel clusters of single tubular halloysite crystals suggests that because of significant [H2O] activity in the environment, halloysite may have been derived from the alteration of rectorite.


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