Investigations about Al and Cu-Based Planar Spiral Inductors on Sapphire for GaN-Based RF Applications

Conventionally, Cu is preferred over Al to fabricate integrated inductors with higher quality factors on either silicon or sapphire substrates, profiting from its lower resistivity. However, after investigating and comparing these two kinds of metal multilayers in terms of fabrication process, electrical conductivity, in-depth profile analysis and performance of actual inductors, the Al-based metal multilayer exhibits competitive ability in fabricating thin-film inductors on sapphire compared to Cu-based multilayers. This is attributed to the degradation in electrical conductivity out of oxidation of Cu-based metal sublayers or forming alloys between them. Furthermore, in order to avoid complicated de-embedding procedures in the characterization of the on-chip inductors, a six-element equivalent physical model, which takes the parasitic effect of radio-frequency (RF) test structures into account, is proposed and validated by matching well with embedded measurement results.

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High Frequency Measurement Techniques for On-Chip Inductors

International Symposium on Microelectronics ◽

10.4071/isom-2010-tha4-paper3 ◽

2010 ◽

Vol 2010 (1) ◽

pp. 000886-000890

Author(s):

Bruce C. Kim ◽

Dae-Hyun Han ◽

Seok-Ho Noh

Keyword(s):

Wireless Communication ◽

Resonance Frequency ◽

High Frequency ◽

Measurement Techniques ◽

Measurement Data ◽

Frequency Measurement ◽

Quality Factors ◽

Wireless Applications ◽

Spiral Inductors ◽

On Chip

This paper presents high frequency measurement techniques of on-chip inductors in giga Hertz range for wireless communication products. The on-chip inductors were fabricated on high resistive substrate to reduce loss. We compared several different on-chip inductors for self-resonance frequency and quality factors. The collection of measurement data could be used for the guideline of designing practical spiral inductors for wireless applications.

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A novel analytical approach to parameter extraction for on-chip spiral inductors taking into account high-order parasitic effect

Solid-State Electronics ◽

10.1016/j.sse.2006.07.018 ◽

2006 ◽

Vol 50 (9-10) ◽

pp. 1557-1562 ◽

Cited By ~ 18

Author(s):

F.Y. Huang ◽

J.X. Lu ◽

D.M. Jiang ◽

X.C. Wang ◽

N. Jiang

Keyword(s):

Analytical Approach ◽

Parameter Extraction ◽

High Order ◽

Spiral Inductors ◽

Parasitic Effect ◽

On Chip

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Low-Process–Voltage–Temperature-Sensitivity Multi-Stage Timing Monitor for System-on-Chip Applications

Electronics ◽

10.3390/electronics10131587 ◽

2021 ◽

Vol 10 (13) ◽

pp. 1587

Author(s):

Duo Sheng ◽

Hsueh-Ru Lin ◽

Li Tai

Keyword(s):

High Performance ◽

Power Reduction ◽

System On Chip ◽

Timing Information ◽

Multi Stage ◽

Dynamic Voltage ◽

And Performance ◽

On Chip ◽

Maximum Measurement ◽

Maximum Measurement Error

High performance and complex system-on-chip (SoC) design require a throughput and stable timing monitor to reduce the impacts of uncertain timing and implement the dynamic voltage and frequency scaling (DVFS) scheme for overall power reduction. This paper presents a multi-stage timing monitor, combining three timing-monitoring stages to achieve a high timing-monitoring resolution and a wide timing-monitoring range simultaneously. Additionally, because the proposed timing monitor has high immunity to the process–voltage–temperature (PVT) variation, it provides a more stable time-monitoring results. The time-monitoring resolution and range of the proposed timing monitor are 47 ps and 2.2 µs, respectively, and the maximum measurement error is 0.06%. Therefore, the proposed multi-stage timing monitor provides not only the timing information of the specified signals to maintain the functionality and performance of the SoC, but also makes the operation of the DVFS scheme more efficient and accurate in SoC design.

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Fuzzy-Based Thermal Management Scheme for 3D Chip Multicores with Stacked Caches

Electronics ◽

10.3390/electronics9020346 ◽

2020 ◽

Vol 9 (2) ◽

pp. 346 ◽

Cited By ~ 1

Author(s):

Lili Shen ◽

Ning Wu ◽

Gaizhen Yan

Keyword(s):

Power Consumption ◽

Thermal Management ◽

System Performance ◽

Control Policy ◽

Three Dimension ◽

Processor Core ◽

Management Scheme ◽

And Performance ◽

On Chip ◽

Silicon Vias

By using through-silicon-vias (TSV), three dimension integration technology can stack large memory on the top of cores as a last-level on-chip cache (LLC) to reduce off-chip memory access and enhance system performance. However, the integration of more on-chip caches increases chip power density, which might lead to temperature-related issues in power consumption, reliability, cooling cost, and performance. An effective thermal management scheme is required to ensure the performance and reliability of the system. In this study, a fuzzy-based thermal management scheme (FBTM) is proposed that simultaneously considers cores and stacked caches. The proposed method combines a dynamic cache reconfiguration scheme with a fuzzy-based control policy in a temperature-aware manner. The dynamic cache reconfiguration scheme determines the size of the cache for the processor core according to the application that reaches a substantial amount of power consumption savings. The fuzzy-based control policy is used to change the frequency level of the processor core based on dynamic cache reconfiguration, a process which can further improve the system performance. Experiments show that, compared with other thermal management schemes, the proposed FBTM can achieve, on average, 3 degrees of reduction in temperature and a 41% reduction of leakage energy.

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