scholarly journals ESD Design and Analysis by Drain Electrode-Embedded Horizontal Schottky Elements for HV nLDMOSs

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 178
Author(s):  
Shi-Zhe Hong ◽  
Shen-Li Chen
Keyword(s):  
Integrated Circuits ◽  
Electrostatic Discharge ◽  
Schottky Diodes ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Good Strategy ◽  
Fabrication Cost ◽  
Esd Protection ◽  
Drain Electrode ◽  
Length Reduction

Electrostatic discharge (ESD) events can severely damage miniature components. Therefore, ESD protection is critical in integrated circuits. In this study, drain-electrode-embedded horizontal Schottky diode contact modulation and Schottky length reduction modulation were performed on a high-voltage 60-V n-channel laterally diffused metal-oxide–semiconductor transistor (nLDMOS) element. The effect of the on-voltage characteristics of cascade Schottky diodes on ESD protection was investigated. By using a transmission-line pulse tester, the trigger voltage, holding voltage, and secondary breakdown current (It2) of the nLDMOS element were determined using the I–V characteristic. As the N+ area was gradually replaced by the parasitic Schottky area at the drain electrode, an equivalent circuit of series Schottky diodes formed, which increased the on-resistance. The larger the Schottky area was the higher the It2 value was. This characteristic can considerably improve the ESD immunity of nLDMOS components (highest improvement of 104%). This is a good strategy for improving ESD reliability without increasing the production steps and fabrication cost.

Suppression of Timing Variations due to Random Dopant Fluctuation by Back-Gate Bias in a Nanometer CMOS Inverter

2020 ◽  
Vol 13 ◽  
Author(s):  
Kai Zhang ◽  
Weifeng Lü ◽  
Peng Si ◽  
Zhifeng Zhao ◽  
Tianyu Yu
Keyword(s):  
Monte Carlo ◽  
Integrated Circuits ◽  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Cmos Inverter ◽  
Back Gate ◽  
Random Dopant Fluctuation ◽  
Random Dopant

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits. Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology. Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG. Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover, that they are also insensitive to channel doping with back-gate bias. Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.

Novel Design of Vertical Double-Diffused Metal–Oxide–Semiconductor Transistor for High Electrostatic Discharge Robustness

2009 ◽  
Vol 48 (4) ◽  
pp. 04C074 ◽  
Author(s):  
Kenichi Hatasako ◽  
Fumitoshi Yamamoto ◽  
Akio Uenishi ◽  
Takashi Kuroi ◽  
Shigeto Maegawa
Keyword(s):  
Metal Oxide ◽  
Electrostatic Discharge ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Novel Design

Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits

2014 ◽  
Vol 13 (02) ◽  
pp. 1450012 ◽  
Author(s):  
Manorama Chauhan ◽  
Ravindra Singh Kushwah ◽  
Pavan Shrivastava ◽  
Shyam Akashe
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Low Power ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
State Dependency ◽  
Low Leakage

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.

Octahedral-Structured Gigantic Precipitates as the Origin of Gate-Oxide Defects in Metal-Oxide-Semiconductor Large-Scale-Integrated Circuits

1996 ◽  
Vol 35 (Part 1, No. 2B) ◽  
pp. 812-817 ◽  
Author(s):  
Manabu Itsumi ◽  
Hideo Akiya ◽  
Takemi Ueki ◽  
Masato Tomita ◽  
Masataka Yamawaki
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Large Scale ◽  
Gate Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Oxide Defects

scholarly journals Sensing and Reliability Improvement of Electrostatic-Discharge Transient by Discrete Engineering for High-Voltage 60-V n-Channel Lateral-Diffused MOSFETs with Embedded Silicon-Controlled Rectifiers

Sensors ◽  
2018 ◽  
Vol 18 (10) ◽  
pp. 3340
Author(s):  
Shen-Li Chen ◽  
Yi-Cih Wu
Keyword(s):  
High Voltage ◽  
Field Effect Transistor ◽  
Electrostatic Discharge ◽  
Reference Sample ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Physical Parameters ◽  
Reliability Improvement ◽  
Drain Side ◽  
Effect Transistor

High-voltage n-channel lateral-diffused metal-oxide-semiconductor field-effect transistor (nLDMOS) components, fabricated by a TSMC 0.25-m 60-V bipolar-CMOS-DMOS (BCD) process with drain-side embedded silicon-controlled rectifier (SCR) of the n-p-n-arranged and p-n-p-arranged types, were investigated, in order to determine the devices’ electrostatic discharge (ESD)-sensing behavior and capability by discrete anode engineering. As for the drain-side n-p-n-arranged type with discrete-anode manners, transmission–line–pulse (TLP) testing results showed that the ESD ability (It2 value) was slightly upgraded. When the discrete physical parameter was 91 rows, the optimal It2 reached 2.157 A (increasing 17.7% compared with the reference sample). On the other hand, the drain-side SCR p-n-p-arranged type with discrete-anode manner had excellent SCR behavior, and its It2 values could be increased to >7 A (increasing >281.9% compared with the reference DUT). Moreover, under discrete anode engineering, the drain-side SCR n-p-n-arranged and p-n-p-arranged types had clearly higher ESD ability, except for the few discrete physical parameters. Therefore, using the anode discrete engineering, the ESD dissipation ability of a high-voltage (HV) nLDMOS with drain-side SCRs will have greater effectiveness.

Fundamentals of SiC-Based Device Processing

MRS Bulletin ◽  
1997 ◽  
Vol 22 (3) ◽  
pp. 42-49 ◽  
Author(s):  
M.R. Melloch ◽  
J.A. Cooper ◽  
D.J. Larkin
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Oxidation Rate ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Processing Technology ◽  
Oxide Semiconductor ◽  
Processing Technologies ◽  
Oxidation Rates ◽  
Polysilicon Gate

Since the commercial availability of SiC substrates in 1990, SiC processing technology has advanced rapidly. There have been demonstrations of monolithic digital and analogue integrated circuits, complementary metal-oxide-semiconductor (CMOS) analog integrated circuits, nonvolatile random-access memories, self-aligned polysilicon-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), and buried-channel polysilicon-gate charge-coupled devices (CCDs). In this article, we review processing technologies for SiC.OxidationA beneficial feature of SiC processing technology is that SiC can be thermally oxidized to form SiO2. When a thermal oxide of thickness x is grown, 0.5x of the SiC surface is consumed, and the excess carbon leaves the sample as CO. Shown in Figure 1 are the oxide thicknesses as a function of time for the Si-face and the C-face of 6H-SiC, and for Si. The oxidation rates are considerably lower for SiC than for Si. The oxidation rate of the C-face of 6H-SiC is considerably greater than that of the Si-face. Hornetz et al. have shown that the reason for the slower oxidation rate of the Si-face is due to a 1-nm Si4C4−xO2 (x < 2) layer that forms between the SiC and the SiO2 during oxidation of the Si-face. When oxidizing the Si-face, the Si atoms oxidize first, which inhibits the oxidation of the underlying C atoms that are 0.063 nm below the Si atoms. When oxidizing the C-face, the C atoms readily oxidize first to form CO, with no formation of the Si4C4−xO2 layer for temperatures above 1000°C.

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