scholarly journals Interleaved High Step-Up DC–DC Converter with Voltage-Lift and Voltage-Stack Techniques for Photovoltaic Systems

Energies ◽  
2020 ◽  
Vol 13 (10) ◽  
pp. 2537
Author(s):  
Shin-Ju Chen ◽  
Sung-Pei Yang ◽  
Chao-Ming Huang ◽  
Yu-Hua Chen

A novel interleaved high step-up DC–DC converter applied for applications in photovoltaic systems is proposed in this paper. The proposed configuration is composed of three-winding coupled inductors, voltage multiplier cells and a clamp circuit. The step-up voltage gain is effectively increased, owing to the voltage-stack and voltage-lift techniques using the voltage multiplier cells. The leakage inductor energy is recycled by the clamp circuit to avoid the voltage surge on a power switch. The low-voltage-rated power switches with low on-state resistances and costs can be used to decrease the conduction losses and increase the conversion efficiency when the voltage stresses of power switches for the converter are considerably lower than the high output voltage. The reverse-recovery problems of diodes are mitigated by the leakage inductances of the coupled inductors. Moreover, both the input current ripple and the current stress on each power switch are reduced, owing to the interleaved operation. The operating principle and steady-state analysis of the proposed converter are thoroughly presented herein. A controller network is designed to diminish the effect of the variations of input voltage and output load on the output voltage. Finally, the experimental results for a 1 kW prototype with 28–380 V voltage conversion are shown to demonstrate its effectiveness and performance.

2020 ◽  
Vol 10 (22) ◽  
pp. 8254
Author(s):  
Javed Ahmad ◽  
Mohammad Zaid ◽  
Adil Sarwar ◽  
Chang-Hua Lin ◽  
Shafiq Ahmad ◽  
...  

In this paper, a new transformerless high voltage gain dc-dc converter is proposed for low and medium power application. The proposed converter has high quadratic gain and utilizes only two inductors to achieve this gain. It has two switches that are operated simultaneously, making control of the converter easy. The proposed converter’s output voltage gain is higher than the conventional quadratic boost converter and other recently proposed high gain quadratic converters. A voltage multiplier circuit (VMC) is integrated with the proposed converter, which significantly increases the converter’s output voltage. Apart from a high output voltage, the proposed converter has low voltage stress across switches and capacitors, which is a major advantage of the proposed topology. A hardware prototype of 200 W of the proposed converter is developed in the laboratory to validate the converter’s performance. The efficiency of the converter is obtained through PLECS software by incorporating the switching and conduction losses.


Processes ◽  
2021 ◽  
Vol 9 (7) ◽  
pp. 1112
Author(s):  
Yu-En Wu ◽  
Jyun-Wei Wang

This study developed a novel, high-efficiency, high step-up DC–DC converter for photovoltaic (PV) systems. The converter can step-up the low output voltage of PV modules to the voltage level of the inverter and is used to feed into the grid. The converter can achieve a high step-up voltage through its architecture consisting of a three-winding coupled inductor common iron core on the low-voltage side and a half-wave voltage doubler circuit on the high-voltage side. The leakage inductance energy generated by the coupling inductor during the conversion process can be recovered by the capacitor on the low-voltage side to reduce the voltage surge on the power switch, which gives the power switch of the circuit a soft-switching effect. In addition, the half-wave voltage doubler circuit on the high-voltage side can recover the leakage inductance energy of the tertiary side and increase the output voltage. The advantages of the circuit are low loss, high efficiency, high conversion ratio, and low component voltage stress. Finally, a 500-W high step-up converter was experimentally tested to verify the feasibility and practicability of the proposed architecture. The results revealed that the highest efficiency of the circuit is 98%.


Author(s):  
Mamidala Hemanth Reddy

The output voltage from the sustainable energy like photovoltaic (PV) arrays and fuel cells will be at less amount of level. This must be boost considerably for practical utilization or grid connection. A conventional boost converter will provides low voltage gain while Quadratic boost converter (QBC) provides high voltage gain. QBC is able to regulate the output voltage and the choice of second inductor can give its current as positive and whereas for boost increases in the voltage will not able to regulate the output voltage. It has low semiconductor device voltage stress and switch usage factor is high. Analysis and design modeling of Quadratic boost converter is proposed in this paper. A power with 50 W is developed with 18 V input voltage and yield 70 V output voltage and the outcomes are approved through recreation utilizing MATLAB/SIMULINK MODEL.


Author(s):  
Suwarno Suwarno ◽  
Tole Sutikno

<p>This paper presents the implementation of the buck-boost converter design which is a power electronics applications that can stabilize voltage, even though the input voltage changes. Regulator to stabilize the voltage using PWM pulse that triger pin 2 on XL6009. In this design of buck-boost converter is implemented using the XL6009, LM7815 and TIP2955. LM7815 as output voltage regulator at 15V with 1A output current, while TIP2955 is able to overcome output current up to 5A. When the LM7815 and TIP2955 are connected in parallel, the converter can increase the output current to 6A.. Testing is done using varied voltage sources that can be set. The results obtained from this design can be applied to PV (Photovoltaic) and WP (Wind Power), with changes in input voltage between 3-21V dc can produce output voltage 15V.</p>


DC-DC converters are playing an important role in designing of Electric Vehicles, integration of solar cells and other DC applications. Contemporary high power applications use multilevel converters that have multi stage outputs for integrating low voltage sources. Conventional DC-DC converters use single source and have complex structure while using for Hybrid Energy Systems. This paper proposes a multi-input, multi-output DC-DC converter to produce constant output voltage at different input voltage conditions. This topology is best suitable for hybrid power systems where the output voltage is variable due to environmental conditions. It reduces the requirement of magnetic components in the circuit and also reduces the switching losses. The proposed topology has two parts namely multi-input boost converter and level-balancing circuit. Boost converter increases the input voltage and Level Balancing Circuit produce Multi output. Equal values of capacitors are used in Level Balancing Circuit to ensure the constant output voltage at all output stages. The operating modes of each part are given and the design parameters of each part are calculated. Performance of the proposed topology is verified using MATLAB/Simulink simulation which shows the correctness of the analytical approach. Hardware is also presented to evaluate the simulation results.


Energies ◽  
2019 ◽  
Vol 12 (3) ◽  
pp. 394 ◽  
Author(s):  
Dai-Van Vo ◽  
Minh-Khai Nguyen ◽  
Duc-Tri Do ◽  
Youn-Ok Choi

A novel single-phase nine-level boost inverter is proposed in this paper. The proposed inverter has an output voltage which is higher than the input voltage by switching capacitors in series and in parallel. The maximum output voltage of the proposed inverter is determined by using the boost converter circuit, which has been integrated into the circuit. The proposed topology is able to invert the multilevel voltage with the high step-up output voltage, simple structure and fewer power switches. In this paper, the circuit configuration, the operating principle, and the output voltage expression have been derived. The proposed converter has been verified by simulation and experiment with the help of PSIM software and a laboratory prototype. The experimental results match the theoretical calculation and the simulation results.


Energies ◽  
2018 ◽  
Vol 11 (10) ◽  
pp. 2640 ◽  
Author(s):  
Xiang Lin ◽  
Faqiang Wang ◽  
Herbert H. C. Iu

Bridgeless power factor correction (PFC) converters have a reduced number of semiconductors in the current flowing path, contributing to low conduction losses. In this paper, a new bridgeless high step-up voltage gain PFC converter is proposed, analyzed and validated for high voltage applications. Compared to its conventional counterpart, the input rectifier bridge in the proposed bridgeless PFC converter is completely eliminated. As a result, its conduction losses are reduced. Also, the current flowing through the power switches in the proposed bridgeless PFC converter is only half of the current flowing through the rectifier diodes in its conventional counterpart, therefore, the conduction losses can be further improved. Moreover, in the proposed bridgeless PFC converter, not only the voltage stress of power switches is lower than the output voltage, but the voltage stress of the output diodes is lower than the conventional counterpart. In addition, this proposed bridgeless PFC converter features a simple circuit structure and high PFC performance. Finally, the proposed bridgeless PFC converter is analyzed and designed in the discontinuous conduction mode (DCM). The simulation results are presented to verify the effectiveness of the proposed bridgeless PFC converter.


2013 ◽  
Vol 273 ◽  
pp. 399-403
Author(s):  
Xiao Yu Zhao ◽  
Cong Wang ◽  
Feng Yang ◽  
Su Ke Wang

A novel topology of isolated input-series and output-series (ISOS) full-bridge bidirectional DC/DC converter is described in this paper for the application requirement of high input voltage and high output voltage, which can be used in the next generation medium and high voltage power conversion systems. The proposed novel isolated bidirectional DC/DC converter not only can apparently decrease the stress of the switches, but also have the advantages, such as galvanic isolation, ease of realizing soft-switching control, high power density, and so on. In this paper, working principle of the proposed DC/DC converter is discussed in detail, the corresponding equations are derived, and the soft switching implementation is discussed too. In the end, simulation is done through PSIM to certify the feasibility of the proposed DC/DC converter and accuracy of the criterion.


2019 ◽  
Vol 29 (01) ◽  
pp. 2050013
Author(s):  
Najmeh Cheraghi Shirazi ◽  
Abumoslem Jannesari ◽  
Pooya Torkzadeh

A new self-start-up switched-capacitor charge pump is proposed for low-power, low-voltage and battery-less implantable applications. To minimize output voltage ripple and improve transient response, interleaving regulation technique is applied to a multi-stage Cross-Coupled Charge Pump (CCCP) circuit. It splits the power flow in a time-sequenced manner. Three cases of study are designed and investigated with body-biasing technique by auxiliary transistors: Four-stage Two-Branch CCCP (TBCCCP), the two-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP2) and four-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP4). Multi-phase nonoverlap clock generator circuit with body-biasing technique is also proposed which can operate at voltages as low as CCCP circuits. The proposed circuits are designed with input voltage as low as 300 to 400[Formula: see text]mV and 20[Formula: see text]MHz clock frequency for 1[Formula: see text]pF load capacitance. Among the three designs, ITBCCCP4 has the lowest ramp-up time (41.6% faster), output voltage ripple (29% less) and power consumption (19% less). The Figure-Of-Merit (FOM) of ITBCCCP4 is the highest value among two others. For 400[Formula: see text]mV input voltage, ITBCCCP4 has a 98.3% pumping efficiency within 11.6[Formula: see text][Formula: see text]s, while having a maximum voltage ripple of 0.1% and a power consumption as low as 2.7[Formula: see text]nW. The FOM is 0.66 for this circuit. The designed circuits are implemented in 180-nm standard CMOS technology with an effective chip area of [Formula: see text][Formula: see text][Formula: see text]m for TBCCCP, [Formula: see text][Formula: see text][Formula: see text]m for ITBCCCP2 and [Formula: see text][Formula: see text][Formula: see text]m for ITBCCCP4.


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