Package on Package (PoP) stacking has become an attractive method for 3D integration to meet the demands of higher functionality in ever smaller packages, especially when coupled with the use of stacked die. To accomplish this, new packaging designs need to be able to integrate more dies with greater function, higher I/O counts, smaller pitches, and greater heat densities, while being pushed into smaller and smaller footprints. A new 3D “Package Interposer Package” (PIP) solution is suitable for combining multiple memory, ASICs, stacked die, stacked packaged die, etc., into a single package. This approach also favors system integration with high density power delivery by appropriate interposer design and thermal management. Traditional Package on Package (PoP) approaches use direct solder connections between the substrates and are limited to use of single (or minimum) die on the bottom substrate, to reduce warpage and improve stability. For PIP, the stability imparted by the interposer reduces warpage, allowing assemblers of the PIP to select the top and bottom components (substrates, die, stacked die, modules) from various suppliers. This mitigates the problem of variation in warpage trends from room temperature to reflow temperature for different substrates/modules when combined with other packages. PIP facilitates more space-efficient designs, and can accommodate any stacked die height without compromising warpage and stability. PIP can accommodate modules with stacked die on organic, ceramic, or silicon board substrates, where each can be detached and replaced without affecting the rest of the package. Thus, PIP will be economical for high-end electronics, since a damaged, non-factional part of the package can be selectively removed and replaced. A variety of interposer structures were used to fabricate Package Interposer Package (PIP) modules. Electrical connections were formed during reflow using a tin-lead eutectic solder paste. Interconnection among substrates (packages) in the stack was achieved using interposers. Plated through holes in the interposers, formed by laser or mechanical drilling and having diameters ranging from 50 μm to 250 μm, were filled with an electrically conductive adhesive and cured. The adhesive-filled and cured interposers were reflowed with circuitized substrates to produce a PIP structure. In summary, the present work describes an integrated approach to develop 3D PIP constructions on various stacked die or stacked packaged die configurations.
Rheologically Assisted Design of Conductive Adhesives for Stencil Printing on PCB
