scholarly journals An Empirical Modeling of Gate Voltage-Dependent Behaviors of Amorphous Oxide Semiconductor Thin-Film Transistors including Consideration of Contact Resistance and Disorder Effects at Room Temperature

Membranes ◽  
2021 ◽  
Vol 11 (12) ◽  
pp. 954
Author(s):  
Sungsik Lee
Keyword(s):  
Contact Resistance ◽  
Gate Voltage ◽  
Room Temperature ◽  
Empirical Modeling ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Channel Conductance ◽  
Disorder Effects ◽  
Amorphous Oxide Semiconductor ◽  
Voltage Dependent

In this paper, we present an empirical modeling procedure to capture gate bias dependency of amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) while considering contact resistance and disorder effects at room temperature. From the measured transfer characteristics of a pair of TFTs where the channel layer is an amorphous In-Ga-Zn-O (IGZO) AOS, the gate voltage-dependent contact resistance is retrieved with a respective expression derived from the current–voltage relation, which follows a power law as a function of a gate voltage. This additionally allows the accurate extraction of intrinsic channel conductance, in which a disorder effect in the IGZO channel layer is embedded. From the intrinsic channel conductance, the characteristic energy of the band tail states, which represents the degree of channel disorder, can be deduced using the proposed modeling. Finally, the obtained results are also useful for development of an accurate compact TFT model, for which a gate bias-dependent contact resistance and disorder effects are essential.

Study on Fabrication and Fast Switching of High Voltage SiC JFET

2013 ◽  
Vol 827 ◽  
pp. 282-286
Author(s):  
Gang Chen ◽  
Song Bai ◽  
Run Hua Huang ◽  
Yong Hong Tao ◽  
Ao Liu
Keyword(s):  
Gate Voltage ◽  
Room Temperature ◽  
Inversion Layer ◽  
Oxide Semiconductor ◽  
Low Loss ◽  
Semiconductor Interface ◽  
Fast Switching ◽  
High Temperature Operation ◽  
Off Time ◽  
Channel Region

SiC devices have excellent properties such as ultra low loss, high withstand voltage, large capacity, high frequency, and high temperature operation compared with Si devices. The SiC JFET is expected to be appropriate for the power device because a JFET has no oxide-semiconductor interface in the channel region and does not use the low mobility SiC MOSFET inversion layer as a channel. Forward I-V up to 4A for SiC VJFET, Gate voltage from 2V to 3.5V by step 0.5V. Reverse I-V characteristics up to 4500V (VG=-8V) for SiC VJFET, Gate voltage from-4V to-8V by step-2V. Turn-off characteristics are studied and fast turn-off time of 136ns at room temperature under DC voltage of 600V is successfully demonstrated.

1.4kV Double-Implanted MOSFETs Fabricated on 4H-SiC(000-1)

2011 ◽  
Vol 679-680 ◽  
pp. 607-612 ◽  
Author(s):  
Hiroshi Kono ◽  
Takuma Suzuki ◽  
Kazuto Takao ◽  
Masaru Furukawa ◽  
Makoto Mizukami ◽  
...  
Keyword(s):  
Room Temperature ◽  
Dielectric Breakdown ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Drain Voltage ◽  
Mos Capacitor ◽  
Time Dependent Dielectric Breakdown ◽  
Blocking Voltage ◽  
Switching Characteristics

1.2 mm × 1.2 mm and 2.7 mm × 2.7 mm silicon carbide double-implanted metal-oxide-semiconductor field-effect transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. 1.2 mm × 1.2 mm DIMOSFETs were characterized from room temperature to 150°C. At room temperature, the specific on-resistance of this MOSFET was 5.7 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The blocking voltage of this MOSFET was 1450 V based on the avalanche current. At 150 °C, the specific on-resistance increased from 5.7 mΩcm2 to 9.1 mΩcm2 and the threshold voltage decreased from 4.9 V to 4.1 V. The blocking voltage increased from 1450V to 1500V. 2.7 mm × 2.7 mm DIMOSFETs were also characterized at room temperature. They showed a specific on-resistance of 8.0 mΩcm2 at a gate bias of 20 V and a drain voltage of 1 V. The blocking voltage of this device was 1550 V, which was determined by the avalanche current. The time-zero dielectric breakdown (TZDB) and time-dependent dielectric breakdown (TDDB) characteristics of 180 μm × 180 μm MOS capacitor were estimated. At room temperature (RT), TZDB was 9.3 MV/cm and the charge to breakdown value of 63% cumulative failure (Qbd) was 72 C/cm2. The temperature dependence of Qbd measurements showed that it deceased from 72 C/cm2 at RT to 14 C/cm2 at 250 °C. Switching characteristics of 1.2 mm × 1.2 mm DIMOSFETs were obtained by the double-pulse measurements. The turn-on time and the turn-off time were 36 nsec and 53 nsec, respectively.

scholarly journals Room-temperature fabrication of light-emitting thin films based on amorphous oxide semiconductor

AIP Advances ◽  
2016 ◽  
Vol 6 (1) ◽  
pp. 015106 ◽  
Author(s):  
Junghwan Kim ◽  
Norihiko Miyokawa ◽  
Keisuke Ide ◽  
Yoshitake Toda ◽  
Hidenori Hiramatsu ◽  
...  
Keyword(s):  
Thin Films ◽  
Room Temperature ◽  
Oxide Semiconductor ◽  
Amorphous Oxide ◽  
Light Emitting ◽  
Amorphous Oxide Semiconductor

A p-Type Amorphous Oxide Semiconductor and Room Temperature Fabrication of Amorphous Oxide p–n Heterojunction Diodes

2003 ◽  
Vol 15 (17) ◽  
pp. 1409-1413 ◽  
Author(s):  
S. Narushima ◽  
H. Mizoguchi ◽  
K. Shimizu ◽  
K. Ueda ◽  
H. Ohta ◽  
...  
Keyword(s):  
Room Temperature ◽  
Oxide Semiconductor ◽  
Amorphous Oxide ◽  
Amorphous Oxide Semiconductor ◽  
Heterojunction Diodes ◽  
P Type

1360 V, 5.0 mΩcm2 Double-Implanted MOSFETs Fabricated on 4H-SiC(000-1)

2010 ◽  
Vol 645-648 ◽  
pp. 987-990 ◽  
Author(s):  
Hiroshi Kono ◽  
Takuma Suzuki ◽  
Makoto Mizukami ◽  
Chiharu Ota ◽  
Shinsuke Harada ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Field Effect ◽  
Room Temperature ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Drain Voltage ◽  
Blocking Voltage

Silicon carbide Double-Implanted Metal-Oxide-Semiconductor Field-Effect Transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. The DIMOSFETs were characterized from room temperature to 250°C. At room temperature, they showed a specific on-resistance of 4.9 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The specific on-resistance taken at a drain current (Id) of 260 A/cm2 was 5.0 mΩcm2. The blocking voltage of this device was higher than 1360 V at room temperature. At 250°C, the specific on-resistance increased from 5.0 mΩcm2 to 12.5 mΩcm2 and the threshold voltage determined at Id = 26 mA/cm2 decreased from 5.5 V to 4.3 V.

Enhanced Seebeck Coefficient of Amorphous Oxide Semiconductor Superlattices

2007 ◽  
Vol 1044 ◽  
Author(s):  
Hiromichi Ohta ◽  
Rong Huang ◽  
Yuichi Ikuhara
Keyword(s):  
Seebeck Coefficient ◽  
Room Temperature ◽  
Pulsed Laser ◽  
Laser Deposition ◽  
Oxide Semiconductor ◽  
High Electrical Conductivity ◽  
Amorphous Oxide ◽  
Substrate Heating ◽  
Amorphous Oxide Semiconductor ◽  
Quantum Size

AbstractWe propose herein that amorphous oxide semiconductor (AOS) superlattices, which can be deposited on various substrate including glasses or plastics without any substrate heating, are appropriate for the realization of superlattice thermoelectric devices. As an example, thermoelectric properties of AOS superlattices composed of a-In-Zn-O (well) and a-In-Ga-Zn-O (barrier) layers, fabricated on SiO2 glass substrate by pulsed laser deposition at room temperature, were measured to clarify whether enhancement of Seebeck coefficient |S| occurs or not. The |S|2D value increases drastically with decreasing a-In-Zn-O thickness (dIZO) when the dIZO is < ∼5 nm, and reached 73 μV·K-1 (dIZO = 0.3 nm), which is ∼4 times larger than that of bulk |S|3D (19 μV·K-1), while it kept high electrical conductivity, clearly demonstrating that the quantum size effect can be utilized in AOS superlattices.

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