scholarly journals Design Optimization of Double-Gate Isosceles Trapezoid Tunnel Field-Effect Transistor (DGIT-TFET)

Micromachines ◽  
2019 ◽  
Vol 10 (4) ◽  
pp. 229
Author(s):  
Hwa Gu ◽  
Sangwan Kim
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Channel Structure ◽  
Double Gate ◽  
Ultra Low Power ◽  
Isosceles Trapezoid ◽  
Technical Issues ◽  
Effect Transistor ◽  
Aided Design

Recently, tunnel field-effect transistors (TFETs) have been regarded as next-generation ultra-low-power semi-conductor devices. To commercialize the TFETs, however, it is necessary to improve an on-state current caused by tunnel-junction resistance and to suppress a leakage current from ambipolar current (IAMB). In this paper, we suggest a novel TFET which features double gate, vertical, and trapezoid isosceles channel structure to solve the above-mentioned technical issues. The device design is optimized by examining its electrical characteristics with the help of technology computer-aided design (TCAD) simulation. As a result, double-gate isosceles trapezoid (DGIT) TFET shows a much better performance than the conventional TFET in terms of ON-state current (ION), IAMB, and gate-to-drain capacitance (CGD). It is confirmed that an inverter composed of DGIT-TFETs can operate with less than 1 ns intrinsic delay time and negligible voltage overshoot.

Surrounding Channel Nanowire Tunnel Field-Effect Transistor with Dual Gate to Reduce a Hump Phenomenon

2020 ◽  
Vol 20 (7) ◽  
pp. 4182-4187
Author(s):  
Ye Sung Kwon ◽  
Seong-Hyun Lee ◽  
Yoon Kim ◽  
Garam Kim ◽  
Jang Hyun Kim ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Control Device ◽  
Subthreshold Region ◽  
Dual Gate ◽  
Technical Issues ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Aided Design

The tunnel field-effect transistor (TFET) with surrounding channel nanowire (SCNW) structure promises better performance than the conventional planar TFET in terms of subthreshold swing (SS) and on-current (ION). In spite of the advantages of SCNW TFET, there are some technical issues in the aspects of a hump phenomenon in subthreshold region and a high ambipolar current (IAMB) in off-state. In order to overcome these issues, a novel dual-gate SCNW TFET (DG-SCNW TFET) with differential gate work functions (WFs) and a gate-drain underlap is proposed and studied by using technology computer-aided design (TCAD) simulation. In addition, a hetero-junction with SiGe source is applied to improve the device performance. Finally, it is confirmed that the optimized DG-SCNW TFET shows the remarkable performance comparing with the control device.

scholarly journals T-Channel Field Effect Transistor with Three Input Terminals (Ti-TcFET)

Micromachines ◽  
2020 ◽  
Vol 11 (1) ◽  
pp. 64
Author(s):  
Zeqi Chen ◽  
Jianping Hu ◽  
Hao Ye ◽  
Zhufei Chu
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Field Effect Transistors ◽  
Structure Design ◽  
Channel Structure ◽  
Oxide Semiconductor ◽  
Back Gate ◽  
Effect Transistor ◽  
Current Characteristics

In this paper, a novel T-channel field effect transistor with three input terminals (Ti-TcFET) is proposed. The channel of a Ti-TcFET consists of horizontal and vertical sections. The top gate is above the horizontal channel, while the front gate and back gate are on either side of the vertical channel. The T-shaped channel structure increases the coupling area between the top gate and the front and back gates, which improves the ability of the gate electrodes to control the channel. What’s more, it makes the top gate have almost the same control ability for the channel as the front gate and the back gate. This unique structure design brings a unique function in that the device is turned on only when two or three inputs are activated. Silvaco technology computer-aided design (TCAD) simulations are used to verify the current characteristics of the proposed Ti-TcFET. The current characteristics of the device are theoretically analyzed, and the results show that the theoretical analysis agrees with the TCAD simulation results. The proposed Ti-TcFET devices with three input terminals can be used to simplify the complex circuits in a compact style with reduced counts of transistors compared with the traditional complementary metal–oxide–semiconductor/ fin field-effect transistors (CMOS/FinFETs) with a single input terminal and thus provides a new idea for future circuit designs.

scholarly journals A Novel Germanium-Around-Source Gate-All-Around Tunnelling Field-Effect Transistor for Low-Power Applications

Micromachines ◽  
2020 ◽  
Vol 11 (2) ◽  
pp. 164
Author(s):  
Ke Han ◽  
Shanglin Long ◽  
Zhongliang Deng ◽  
Yannan Zhang ◽  
Jiawei Li
Keyword(s):  
Low Power ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Field Effect Transistors ◽  
Electrical Characteristics ◽  
Source Voltage ◽  
Effect Transistor ◽  
Supply Current ◽  
Aided Design

This paper presents a germanium-around-source gate-all-around tunnelling field-effect transistor (GAS GAA TFET). The electrical characteristics of the device were studied and compared with those of silicon gate-all-around and germanium-based-source gate-all-around tunnel field-effect transistors. Furthermore, the electrical characteristics were optimised using Synopsys Sentaurus technology computer-aided design (TCAD). The GAS GAA TFET contains a combination of around-source germanium and silicon, which have different bandgaps. With an increase in the gate-source voltage, band-to-band tunnelling (BTBT) in silicon rapidly approached saturation since germanium has a higher BTBT probability than silicon. At this moment, germanium could still supply current increment, resulting in a steady and steep average subthreshold swing ( S S AVG ) and a higher ON-state current. The GAS GAA TFET was optimised through work function and drain overlapping engineering. The optimised GAS GAA TFET exhibited a high ON-state current ( I ON ) (11.9 μ A), a low OFF-state current ( I OFF ) ( 2.85 × 10 − 9 μ A), and a low and steady S S AVG (57.29 mV/decade), with the OFF-state current increasing by 10 7 times. The GAS GAA TFET has high potential for use in low-power applications.

Optimizing the Screen-Grid Field Effect Transistor for high drive current and low Miller capacitance

2009 ◽  
Vol 1174 ◽  
Author(s):  
Yasaman Shadrokh ◽  
Kristel Fobelets ◽  
Enrique Velazquez-Perez
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Degrees Of Freedom ◽  
Field Effect Transistors ◽  
Switching Speed ◽  
High Drive ◽  
Gate Control ◽  
Effect Transistor ◽  
Screen Grid ◽  
Aided Design

AbstractReduction of parasitic capacitances and improvement of the on-off current ratio (ION/IOFF) can be achieved by increasing the gate control in Field Effect Transistors (FETs). Multiple gated FETs (MugFETs) lend themselves well for this. The MugFET investigated in this manuscript is the Screen Grid FET (SGrFET) that consists of multiple gate cylinders inside the channel perpendicular to the current flow. In this work we illustrate, using 2D Technology Computer Aided Design (TCAD), that the multiple geometrical degrees of freedom of the SGrFET can be exploited to simultaneously optimise the on-current, ION and the gate-drain Miller parasitic capacitance for increased switching speed.

scholarly journals Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 454
Author(s):  
You Wang ◽  
Yu Mao ◽  
Qizheng Ji ◽  
Ming Yang ◽  
Zhaonian Yang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Computer Aided Design ◽  
Field Effect ◽  
Electrostatic Discharge ◽  
Field Effect Transistors ◽  
Test Method ◽  
Current Path ◽  
Simulation Results ◽  
Current Characteristics ◽  
Aided Design

Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure current was 13.3% higher than Conventional TFET. After analyzing the simulation results, the parameters of the SiGe PNN TFET were optimized. The single current path of the SiGe PNN TFET was analyzed and explained in the case of gate grounding.

Temperature Sensitivity Analysis of Extended Source Double Gate Tunnel Field Effect Transistor

2021 ◽  
Author(s):  
Dharmender Nishad ◽  
Kaushal Nigam ◽  
Satyendra Kumar
Keyword(s):  
Temperature Sensitivity ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Effect Of Temperature ◽  
Double Gate ◽  
Extended Source ◽  
Temperature Variations ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

Abstract Temperature-induced performance variation is one of the main concerns of the conventional stack gate oxide double gate tunnel field-effect transistor (SGO-DG-TFET). In this regard, we investigate the temperature sensitivity of extended source double gate tunnel field-effect transistor (ESDG-TFET). For this, we have analyzed the effect of temperature variations on the transfer characteristics, analog/RF, linearity and distortion figure of merits (FOMs) using technology computer aided design (TCAD) simulations. Further, the temperature sensitivity performance is compared with conventional SGO-DG-TFET. The comparative analysis shows that ESDG-TFET is less sensitive to temperature variations compared to the conventional SGO-DG-TFET. Therefore, this indicates that ESDG-TFET is more reliable for low-power, high-frequency applications at a higher temperature compared to conventional SGO-DG-TFET.

scholarly journals Demonstration of Fin-Tunnel Field-Effect Transistor with Elevated Drain

Micromachines ◽  
2019 ◽  
Vol 10 (1) ◽  
pp. 30 ◽  
Author(s):  
Jang Hyun Kim ◽  
Hyun Woo Kim ◽  
Garam Kim ◽  
Sangwan Kim ◽  
Byung-Gook Park
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Electrical Performance ◽  
Control Group ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Tcad Simulation ◽  
High Level ◽  
Aided Design

In this paper, a novel tunnel field-effect transistor (TFET) has been demonstrated. The proposed TFET features a SiGe channel, a fin structure and an elevated drain to improve its electrical performance. As a result, it shows high-level ON-state current (ION) and low-level OFF-state current (IOFF); ambipolar current (IAMB). In detail, its ION is enhanced by 24 times more than that of Si control group and by 6 times more than of SiGe control group. The IAMB can be reduced by up to 900 times compared with the SiGe control group. In addition, technology computer-aided design (TCAD) simulation is performed to optimize electrical performance. Then, the benchmarking of ON/OFF current is also discussed with other research group’s results.

scholarly journals Random Dopant Fluctuation-Induced Variability in n-Type Junctionless Dual-Metal Gate FinFETs

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 282 ◽  
Author(s):  
Liang Dai ◽  
Weifeng Lü ◽  
Mi Lin
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Drain Voltage ◽  
Metal Gate ◽  
Random Dopant Fluctuation ◽  
Computer Aided ◽  
Dual Metal ◽  
Aided Design ◽  
Random Dopant

We investigate the effect of random dopant fluctuation (RDF)-induced variability in n-type junctionless (JL) dual-metal gate (DMG) fin field-effect transistors (FinFETs) using a 3D computer-aided design simulation. We show that the drain voltage (VDS) has a significant impact on the electrostatic integrity variability caused by RDF and is dependent on the ratio of gate lengths. The RDF-induced variability also increases as the length of control gate near the source decreases. Our simulations suggest that the proportion of the gate metal near the source to the entire gate should be greater than 0.5.

Sign in / Sign up

Export Citation Format

Share Document